34921 datasheet(24/36 Pages) FREESCALE

24 / 36 page

Analog Integrated Circuit Device Data

Freescale Semiconductor

34921

FUNCTIONAL DESCRIPTION

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

V3.3, VCORE, B+, and TSD have both positive- and negative-

going thresholds.

Static Operating Specifications

The state of RST is guaranteed as long as the minimum

supervisor operating conditions of B+

≥ 9.0 V and V5.0 ≥

2.0 V and V3.3 ≥ 1.5 V and VCORE are met. Once all these

conditions are met, RST is dependent on system operating

conditions. During initial power-up, RST is held low if any one

of the following error conditions is present: +5.0 V(low),

VCORE(low), +3.3 V(low), B+(low), or TSD. Once all voltages

reach their positive-going threshold, RST is set high after the

appropriate timing.

Dynamic Operating Specifications

The RST is a bidirectional signal with an open drain output

driver and a CMOS digital input gate (see Figure 12). This I/

O structure allows wired OR connection to the CPU’s RST I/

O terminal, as well as allowing the CPU to initiate a reset

cycle by driving its RST terminal low. When responding to a

CPU request for a reset cycle, the 34921 IC must respond

rapidly enough to prevent a glitch. Figure 6, RST Timing,

page 17, shows the timing parameters for responding to an

externally applied RST signal.

Figure 12. RST Terminal Interface

The rise time with the open drain circuit may be relatively

slow, and the internal RST input gate must operate reliably

(no oscillations during the transition) under these conditions;

i.e., the RST input can be inhibited for up to tphsl (max). Error

conditions must be present for a minimum time, tfilter, before

the 34921 responds to them. Once all error conditions are

cleared, RST is held low for an additional time of tdelay,

128 SCLK periods. If any monitored item falls below its

negative-going threshold for t filter, 1.5 µs to 5.0 µs, the tdelay

count is restarted when system operating conditions are met,

regardless of whether the tdelay count has been completed.

The trigger for the tdelay retriggerable one shot is

([+5.0 V(low) + 3.3 V(low) + VCORE (low) + B+(low) + TSD]

and tfilter), where tfilter is the 1.5 µs to 5.0 µs delay.

RST and Thermal Shutdown State (TSD) Definition

There are seven registers in the INFO output word where

the trigger for the reset is recorded. This includes externally

generated resets as well as all the fault conditions listed in the

Supervisory Functions section of this datasheet. These

registers will remain valid as long as B+

≥ 9.0 V. The fault

registers will only be cleared upon an externally generated

RST

and will not be guaranteed for B+ < 9.0 V; i.e., initial

power-up or a serious B+ fault. The EXT bit will only be set

upon an externally generated reset.

Whenever RST is asserted and TSD is not set, the MISO

terminal will enter a high-impedance state, all the step motor

outputs will be off, and all the DC motor low-side drives will

be on. In addition, all internal data registers excepting the

RST

fault registers in the INFO output word will be set to their

default values.

The thermal shutdown circuitry will monitor the chip’s

internal temperature at various points. The overtemperature

circuitry will disable all circuitry on the 34921 IC with the

exception of the RST output. RST will be asserted when the

temperature exceeds 140°C. This condition will be

maintained (regulators shut down in accordance with

Table 6, page 24) until the die temperature falls by the

thermal hysteresis amount, at which time the 5.0 V and 3.3 V

regulators will restart and the supervisor circuit will issue a full

length reset pulse. The system will then perform a normal

restart. The purpose of this circuitry is to prevent damage to

the 34921 owing to inadvertent high dissipation in the motor

drivers.

Table 6. Regulator Shutdown Schedule

ANALOG ENCODER INTERFACE

Introduction

The analog encoder interface is intended to provide a

complete interface for an analog quadrature encoder, such

as an Agilent Technologies HEDS-9710/HEDS-9711 series

of analog output small optical encoder modules.

From

Internal

Reset

Circuits

To Internal

Registers

RST

CLOAD

Optional

Condition

XDCMA(26)

XDCMB(26)

5.0 V

VCORE 3.3 V

Fault Registers

Other Data

Registers

RST

OFF

Updated at falling RST

Default value

TSD and RST

OFF

Updated at falling RST

Default value

TSDCore and RST

OFF

Updated at falling RST

Default value

Notes

26.

XDCMA and XDCMB: 0 means low-side ON, 1 means high-side ON, Z means both OFF.

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