MC68HC11P2BCFN4 datasheet(13/268 Pages) FREESCALE

13 / 268 page

MC68HC11P2 — Rev 1.0

Technical Data

List of Figures

Technical Data — MC68HC11P2

List of Figures

Figure

Title

Page

1-1

MC68HC11P2/MC68HC711P2 block diagram . . . . . . . . . . . . . 19

2-1

84-pin PLCC/CERQUAD pinout . . . . . . . . . . . . . . . . . . . . . . . . 22

2-2

External reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2-3

Oscillator connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2-4

PLL circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2-5

RAM stand-by connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3-1

MC68HC11P2 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3-2

RAM and register overlap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5-1

SCI baud rate generator circuit diagram. . . . . . . . . . . . . . . . . . 88

5-2

SCI1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

5-3

Interrupt source resolution within SCI. . . . . . . . . . . . . . . . . . . 103

6-1

MI BUS timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

6-2

Biphase coding and error detection . . . . . . . . . . . . . . . . . . . . 113

6-3

MI BUS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

6-4

A typical interface between the MC68HC11P2 and the MI BUS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

7-1

SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

7-2

SPI transfer format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

8-1

Timer clock divider chains . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

8-2

Capture/compare block diagram. . . . . . . . . . . . . . . . . . . . . . . 141

8-3

Pulse accumulator block diagram. . . . . . . . . . . . . . . . . . . . . .159

8-4

PWM timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

8-5

PWM duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

9-1

A/D converter block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 174

9-2

Electrical model of an A/D input pin (in sample mode) . . . . . . 175

9-3

A/D conversion sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

10-1

Processing flow out of reset (1 of 2) . . . . . . . . . . . . . . . . . . . . 206

Freescale Semiconductor, Inc.

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