AD9865BCPRL datasheet(11/48 Pages) AD

11 / 48 page

AD9865

Rev. A | Page 11 of 48

Pin No.

Mnemonic

Mode1

Description

TXCLK

ADIO Sample Clock Input

TXQUIET

Fast TxDAC/IAMP Power-Down

RXCLK

ADIO Request Clock Input

Rx and Tx Clock Output at 2 x fADC

17, 64

DRVDD

Digital Output Driver Supply Input

18, 63

DRVSS

Digital Output Driver Supply Return

CLKOUT1

fADC/N Clock Output (L = 1, 2, 4, or 8)

SDIO

Serial Port Data Input/Output

SDO

Serial Port Data Output

SCLK

Serial Port Clock Input

SEN

Serial Port Enable Input

GAIN

Tx Data Port (Tx[5:0]) Mode Select

PGA[5]

HD or FD

MSB of PGA Input Data Port

25 to 29

PGA[4 to 0]

HD or FD

Bits 4 to 0 of PGA Input Data Port

RESET

Reset Input (Active Low)

31, 34, 36, 39, 44, 47, 48

AVSS

Analog Ground

32, 33

REFB, REFT

ADC Reference Decoupling Nodes

35, 40, 43

AVDD

Analog Power Supply Input

37, 38

RX−, RX+

Receive Path − and + Analog Inputs

REFADJ

TxDAC Full-Scale Current Adjust

REFIO

TxDAC Reference Input/Output

IOUT_G−

−Tx Amp Current Output_Sink

IOUT_N−

−Tx Mirror Current Output_Sink

IOUT_G+

+Tx Amp Current Output_Sink

IOUT_N+

+Tx Mirror Current Output_Sink

IOUT_P−

−TxDAC Current Output_Source

IOUT_P+

+TxDAC Current Output_Source

MODE

Digital Interface Mode Select Input

LOW = HD, HIGH = FD

CONFIG

Power-Up SPI Register Default Setting Input

CLKVSS

Clock Oscillator/Synthesizer Supply Return

XTAL

Crystal Oscillator Inverter Output

OSCIN

Crystal Oscillator Inverter Input

CLKVDD

Clock Oscillator/Synthesizer Supply

DVSS

Digital Supply Return

DVDD

Digital Supply Input

CLKOUT2

fOSCIN/L Clock Output, (L = 1, 2, or 4)

PWR_DWN

Power-Down Input

1 HD = half-duplex mode; FD = full-duplex mode.

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