AD9865BCPRL datasheet(8/48 Pages) AD

tên linh kiện	AD9865BCPRL

Giải thích chi tiết về linh kiện	Broadband Modem Mixed-Signal Front End

PDF	48 Pages

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nhà sản xuất	AD [Analog Devices]

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AD9865

Rev. A | Page 8 of 48

FULL-DUPLEX DATA INTERFACE (Tx AND Rx PORT) TIMING SPECIFICATIONS

AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted.

Table 7.

Parameter

Temp

Test Level

Min

Typ

Max

Unit

Tx PATH INTERFACE (See Figure 53)

Input Nibble Rate (2× Interpolation)

Full

160

MSPS

Input Nibble Rate (4× Interpolation)

Full

100

MSPS

Tx Data Setup Time (tDS)

Full

2.5

Tx Data Hold Time (tDH)

Full

1.5

Rx PATH INTERFACE1 (See Figure 54)

Output Nibble Rate

Full

160

MSPS

Rx Data Valid Time (tDV)

Full

Rx Data Hold Time (tDH)

Full

1 CLOAD =5 pF for digital data outputs.

EXPLANATION OF TEST LEVELS

100% production tested.

100% production tested at 25°C and guaranteed by design and characterization at specified temperatures.

III

Sample tested only.

Parameter is guaranteed by design and characterization testing.

Parameter is a typical value only.

100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.

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