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AD9865BCPRL bảng dữ liệu(PDF) 7 Page - Analog Devices

tên linh kiện AD9865BCPRL
Giải thích chi tiết về linh kiện  Broadband Modem Mixed-Signal Front End
PDF  48 Pages
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Trang chủ  http://www.analog.com
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AD9865
Rev. A | Page 7 of 48
SERIAL PORT TIMING SPECIFICATIONS
AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted.
Table 5.
Parameter
Temp
Test Level
Min
Typ
Max
Unit
WRITE OPERATION (See Figure 46)
SCLK Clock Rate (fSCLK)
Full
IV
32
MHz
SCLK Clock High (tHI)
Full
IV
14
ns
SCLK Clock Low (tLOW)
Full
IV
14
ns
SDIO to SCLK Setup Time (tDS)
Full
IV
14
ns
SCLK to SDIO Hold Time (tDH)
Full
IV
0
ns
SEN to SCLK Setup Time (tS)
Full
IV
14
ns
SCLK to SEN Hold Time (tH)
Full
IV
0
ns
READ OPERATION (See Figure 47 and Figure 48)
SCLK Clock Rate (fSCLK)
Full
IV
32
MHz
SCLK Clock High (tHI)
Full
IV
14
ns
SCLK Clock Low (tLOW)
Full
IV
14
ns
SDIO to SCLK Setup Time (tDS)
Full
IV
14
ns
SCLK to SDIO Hold Time (tDH)
Full
IV
0
ns
SCLK to SDIO (or SDO) Data Valid Time (tDV)
Full
IV
14
ns
SEN to SDIO Output Valid to Hi-Z (tEZ)
Full
IV
2
ns
HALF-DUPLEX DATA INTERFACE (ADIO PORT) TIMING SPECIFICATIONS
AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted.
Table 6.
Parameter
Temp
Test Level
Min
Typ
Max
Unit
READ OPERATION1 (See Figure 50)
Output Data Rate
Full
II
5
80
MSPS
Three-State Output Enable Time (tPZL)
Full
II
3
ns
Three-State Output Disable Time (tPLZ)
Full
II
3
ns
Rx Data Valid Time (tVT)
Full
II
1.5
ns
Rx Data Output Delay (tOD)
Full
II
4
ns
WRITE OPERATION (See Figure 49)
Input Data Rate (1× Interpolation)
Full
II
20
80
MSPS
Input Data Rate (2× Interpolation)
Full
II
10
80
MSPS
Input Data Rate (4× Interpolation)
Full
II
5
50
MSPS
Tx Data Setup Time (tDS)
Full
II
1
ns
Tx Data Hold Time (tDH)
Full
II
2.5
ns
Latch Enable Time (tEN)
Full
II
3
ns
Latch Disable Time (tDIS)
Full
II
3
ns
1 CLOAD = 5 pF for digital data outputs.



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