AD9957SLASHPCBZ datasheet(41/60 Pages) AD

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AD9957

Rev. 0 | Page 41 of 60

which three AD9957s are synchronized with one device operating

as a master timing unit and the others as slave units.

The master device must have its SYNC_IN pins included as part

of the synchronization distribution and delay equalization mecha-

nism for it to be synchronized with the slave units.

The synchronization mechanism begins with the clock distribu-

tion and delay equalization block, which ensures that all devices

receive an edge aligned REFCLK signal. However, even though

the REFCLK signal is edge aligned among all devices, this alone

does not guarantee that the clock state of each internal clock

generator is coordinated with the others. This is the role of the

synchronization and delay equalization block. This block accepts

the SYNC_OUT signal generated by the master device and

redistributes it to the SYNC_IN input of the slave units (as well

as feeding it back to the master). The goal of the redistributed

SYNC_OUT signal from the master device is to deliver an edge

aligned SYNC_IN signal to all of the sync receivers.

Assuming that all devices share the same REFCLK edge (due to

the clock distribution and delay equalization block) and that all

devices share the same SYNC_IN edge (due to the synchroniza-

tion and delay equalization block), then all devices should be

generating an internal sync pulse in unison (assuming they all

have the same sync receiver delay value). With the further

stipulation that all devices have the same sync state preset value,

then the synchronized sync pulses cause all of the devices to

assume the same predefined clock state simultaneously. That is,

the internal clocks of all devices are fully synchronized.

The synchronization mechanism depends on the reliable

generation of a sync pulse by the edge detection block in the

sync receiver. Generation of a valid sync pulse, however,

requires proper sampling of the rising edge of the delayed

sync-in signal with the rising edge of the local SYSCLK. If the

edge timing of these signals fails to meet the setup or hold time

requirements of the internal latches in the edge detection

circuitry, then the proper generation of the sync pulse is in

jeopardy. The setup-and-hold validation block (see Figure 58)

gives the user a means to validate that proper edge timing exists

between the two signals. The setup-and-hold validation block

can be disabled via the sync timing validation disable bit in Control

Function Register 2.

The validation block makes use of a user-specified time window

(programmable in increments of ~150 ps via the 4-bit sync

validation delay word in the multichip sync register). The setup

validation and hold validation circuits use latches identical to

those in the rising edge detector and strobe generator. The

programmable time window is used to skew the timing between

the rising edges of the local SYSCLK signal and the rising edges

of the delayed sync-in signal. If either the hold or setup valida-

tion circuits fail to detect a valid edge sample, the condition is

indicated externally via the SYNC_SMP_ERR pin (active high).

The user must choose a sync validation delay value that is a

reasonable fraction of the SYSCLK period. For example, if the

SYSCLK frequency is 1 GHz (1 ns period), then a reasonable

value is 1 or 2 (150 ps or 300 ps). Choosing too large a value can

cause the SYNC_SMP_ERR pin to generate false error signals.

Choosing too small a value may cause instability.

SYNC

PULSE

SYSCLK

DELAY

SYNC VALIDATION

DELAY

SYNC_SMP_ERR

SYNC RECEIVER

SYNC TIMING VALIDATION DISABLE

SETUP

VALIDATION

HOLD

VALIDATION

SETUP AND HOLD VALIDATION

CLOCK

GENERATION

LOGIC

FROM

SYNC

RECEIVER

DELAY

LOGIC

RISING EDGE

DETECTOR

AND STROBE

GENERATOR

Figure 58. Sync Timing Validation Block

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