AD9869BCPZ datasheet(8/36 Pages) AD

8 / 36 page

AD9869

Rev. 0 | Page 8 of 36

HALF-DUPLEX DATA INTERFACE (ADIO PORT) TIMING SPECIFICATIONS

AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted.

Table 6.

Parameter

Temp

Test Level1

Min

Typ

Max

Unit

READ OPERATION2 (See Figure 9)

Output Data Rate

Full

MSPS

Three-State Output Enable Time (tPZL)

Full

Three-State Output Disable Time (tPLZ)

Full

Rx Data Valid Time (tVT)

Full

1.5

Rx Data Output Delay (tOD)

Full

WRITE OPERATION (See Figure 8)

Input Data Rate (2× Interpolation)

Full

MSPS

Input Data Rate (4× Interpolation)

Full

MSPS

Tx Data Setup Time (tDS)

Full

Tx Data Hold Time (tDH)

Full

2.5

Latch Enable Time (tEN)

Full

Latch Disable Time (tDIS)

Full

1 See the Explanation of Test Levels section.

2 CLOAD = 5 pF for digital data outputs.

FULL-DUPLEX DATA INTERFACE (Tx AND Rx PORT) TIMING SPECIFICATIONS

AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted.

Table 7.

Parameter

Temp

Test Level1

Min

Typ

Max

Unit

Tx PATH INTERFACE (See Figure 12)

Input Nibble Rate (2× Interpolation)

Full

160

MSPS

Input Nibble Rate (4× Interpolation)

Full

100

MSPS

Tx Data Setup Time (tDS)

Full

2.5

Tx Data Hold Time (tDH)

Full

1.5

Rx PATH INTERFACE2 (See Figure 13)

Output Nibble Rate

Full

160

MSPS

Rx Data Valid Time (tDV)

Full

Rx Data Hold Time (tDH)

Full

1 See the Explanation of Test Levels section.

2 CLOAD = 5 pF for digital data outputs.

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