TMG39921 datasheet(64/96 Pages) OSRAM

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ams Datasheet

Page 63

[v1-06] 2018-Feb-27

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TMG3992 − Register Description

Configuration Register A0 (CONFIG_A0),

IRBeam Mode

While IRBeam is enabled, PBEN =1, the CONFIG_A0 register is

used for IRBeam control bit configuration.

Figure 64:

Configuration Register A0

The ISQZT bit field defines the length of time between symbols

pin. The LDR pin is set to the level defined by the ISQZL bit. The

following equation governs the time delay:

765

432

Reserved

PBIEN

SLEW

ISQZL

ISQZT

Field

Bits

Description

Reserved

7:6

Reserved. Bits must be set to 0 in IRBeam mode.

PBIEN

Pattern Burst interrupt enable. When PBIEN = 1 the IRBeam interrupt is

enabled.

SLEW

Slew Rate Control. Always =0, unless in IRBeam mode with IBT register value

less than 0x02. Slew is used to maintain LED pulse symmetry.

ISQZL

IRBeam Symbol Quiet Zone LDR Logic state. When ISQZL = 1 and ISQZT > 0,

LDR pin drives low with each “0” RAM pattern bit.

ISQZT

2:0

IRBeam Symbol Quiet Zone Time. This time period represents the number of

bit-times of quiet zone before and after the RAM bit pattern (symbol) is run.

FIELD VALUE

IRBeam Symbol Quiet Zone Time

000

0 bit-times (Not activated)

001

5 bit-times

010

9 bit-times

….

Number of Bit Times =

….

111

257 bit-times

ISQZT

(EQ4)

tISQZT

ISQZT

() tIBT

⋅

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