TMD27721 datasheet(38/60 Pages) OSRAM

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ams Datasheet

Page 37

[v1-21] 2016-Feb-16

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TMD2772/ TMD2772WA − Register Description

Configuration Register (0x0D)

The Configuration Register sets the proximity LED drive level,

wait long time, and ALS gain level

Figure 40:

Configuration Register.

Proximity Pulse Count Register (0x0E)

The Proximity Pulse Count Register sets the number of

proximity pulses that the LDR pin will generate during the Prox

Accum state. The pulses are generated at a 62.5kHz rate.

Figure 41:

Proximity Pulse Count Register

Reserved

AGL

WLONG

PDL

Field

Bits

Description (Reset value = 0x00)

Reserved

7:3

Reserved. Write as 0.

AGL

ALS Gain Level. When asserted, the 1× and 8× ALS gain (AGAIN) modes

are scaled by 0.16. Otherwise, AGAIN is scaled by 1. Should be set = 0

anytime AGAIN is greater than 8x, or if using a TMD module.

WLONG

Wait Long. When asserted, the wait cycles are increased by a factor 12x

from that programmed in the WTIME register.

PDL

Proximity drive level. When asserted, the proximity LDR drive current is

reduced by 9.

PPULSE

Field

Bits

Description

PPULSE

7:0

Proximity Pulse Count. Specifies the number of proximity pulses

to be generated.

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