DP83848C_07 datasheet(12/82 Pages) NSC

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1.5 Reset and Power Down

1.6 Strap Options

The DP83848C uses many of the functional pins as strap

options. The values of these pins are sampled during reset

and used to strap the device into specific modes of opera-

tion. The strap option pin assignments are defined below.

The functional pin name is indicated in parentheses.

A 2.2 k

Ω resistor should be used for pull-down or pull-up to

change the default strap option. If the default option is

required, then there is no need for external pull-up or pull

down resistors. Since these pins may have alternate func-

tions after reset is deasserted, they should not be con-

nected directly to VCC or GND.

Signal Name

Type

Pin #

Description

RESET_N

I, PU

RESET: Active Low input that initializes or re-initializes the

DP83848C. Asserting this pin low for at least 1

µs will force a reset

process to occur. All internal registers will re-initialize to their de-

fault states as specified for each bit in the Register Block section.

All strap options are re-initialized as well.

PWR_DOWN/INT

I, OD, PU

See Section 5.5 for detailed description.

The default function of this pin is POWER DOWN.

POWER DOWN: The pin is an active low input in this mode and

should be asserted low to put the device in a Power Down mode.

INTERRUPT: The pin is an open drain output in this mode and will

be asserted low when an interrupt condition occurs. Although the

pin has a weak internal pull-up, some applications may require an

external pull-up resister. Register access is required for the pin to

be used as an interrupt mechanism. See Section 5.5.2 Interrupt

Mechanism for more details on the interrupt mechanisms.

Signal Name

Type

Pin #

Description

PHYAD0 (COL)

PHYAD1 (RXD_0)

PHYAD2 (RXD_1)

PHYAD3 (RXD_2)

PHYAD4 (RXD_3)

S, O, PU

S, O, PD

PHY ADDRESS [4:0]: The DP83848C provides five PHY ad-

dress pins, the state of which are latched into the PHYCTRL reg-

ister at system Hardware-Reset.

The DP83848C supports PHY Address strapping values 0

(<00000>) through 31 (<11111>). A PHY Address of 0 puts the

part into the MII Isolate Mode. The MII isolate mode must be se-

lected by strapping Phy Address 0; changing to Address 0 by reg-

ister write will not put the Phy in the MII isolate mode. Please refer

to section 2.3 for additional information.

PHYAD0 pin has weak internal pull-up resistor.

PHYAD[4:1] pins have weak internal pull-down resistors.

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