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DP83848C bảng dữ liệu(PDF) 36 Page - National Semiconductor (TI) |
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DP83848C bảng dữ liệu(HTML) 36 Page - National Semiconductor (TI) |
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36 / 82 page ![]() 36 www.national.com 6.0 Reset Operation The DP83848C includes an internal power-on reset (POR) function and does not need to be explicitly reset for normal operation after power up. If required during normal opera- tion, the device can be reset by a hardware or software reset. 6.1 Hardware Reset A hardware reset is accomplished by applying a low pulse (TTL level), with a duration of at least 1 µs, to the RESET_N. This will reset the device such that all registers will be reinitialized to default values and the hardware con- figuration values will be re-latched into the device (similar to the power-up/reset operation). 6.2 Software Reset A software reset is accomplished by setting the reset bit (bit 15) of the Basic Mode Control Register (BMCR). The period from the point in time when the reset bit is set to the point in time when software reset has concluded is approx- imately 1 µs. The software reset will reset the device such that all regis- ters will be reset to default values and the hardware config- uration values will be maintained. Software driver code must wait 3 µs following a software reset before allowing further serial MII operations with the DP83848C. |
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