7.3 Feature Description

7.3.1 PWM Operation and D-CAP3™ Control Mode

The main control loop of the buck is an adaptive on-time pulse width modulation (PWM) controller that supports

a proprietary D-CAP3 control mode. The D-CAP3 control mode combines adaptive on-time control with an

internal compensation circuit for pseudo-fixed frequency and low external component count configuration with

both low-ESR and ceramic output capacitors. The device is stable even with virtually no ripple at the output. The

TPSM861253 also includes an error amplifier that makes the output voltage very accurate.

At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after an

internal one-shot timer expires. This one-shot duration is set proportional to the output voltage, VOUT, and is

inversely proportional to the converter input voltage, VIN, to maintain a pseudo-fixed frequency over the input

voltage range, hence, called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET

is turned on again when the feedback voltage falls below the reference voltage. An internal ripple generation

circuit is added to reference voltage to emulate the output ripple, enabling the use of very low-ESR output

capacitors such as multi-layered ceramic caps (MLCC). No external current sense network or loop compensation

is required for D-CAP3 control mode.

7.3.2 Soft Start and Prebiased Soft Start

The TPSM861253 has an internal fixed 1.6ms soft-start time. The EN default status is low. When the EN pin

becomes high, the internal soft-start function begins ramping up the reference voltage to the PWM comparator.

If the output capacitor is prebiased at start-up, the devices initiate switching and start ramping up only after the

internal reference voltage becomes higher than the feedback voltage, VFB. This scheme makes sure that the

converter ramps up smoothly into the regulation point.

7.3.3 Overvoltage Protection

The TPSM861253 has the overvoltage protection feature. When the output voltage becomes higher than the

OVP threshold, the OVP is triggered with a 24μs deglitch time. Both the high-side MOSFET and the low-side

MOSFET drivers are turned off. When the overvoltage condition is removed, the device returns to switching.

7.3.4 Large Duty Operation

The TPSM861253 can support large duty operations up to 95% by smoothly dropping down the switching

frequency. When VIN / VOUT < 1.6 and VFB is lower than internal VREF, the switching frequency is allowed

to smoothly drop to make tON extended to implement the large duty operation and keep output voltage. The

minimum switching frequency is limited to approximately 600kHz.

7.3.5 Current Protection and Undervoltage Protection

The output overcurrent limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch

current is monitored during the off state by measuring the low-side FET drain-to-source voltage. This voltage is

proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated.

During the on time of the high-side FET switch, the switch current increases at a linear rate determined by the

following:

• VIN

• VOUT

• On time

• Output inductor value

During the on time of the low-side FET switch, this current decreases linearly. The average value of the switch

current is the load current, IOUT. If the monitored valley current is above the OCL level, the converter maintains a

low-side FET on and delays the creation of a new set pulse, even the voltage feedback loop requires one, until

the current level becomes OCL level or lower. In subsequent switching cycles, the on time is set to a fixed value

and the current is monitored in the same manner.

TPSM861253

SLUSFD2A – SEPTEMBER 2023 – REVISED JANUARY 2024

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