TMS320C6421 datasheet(99/227 Pages) TI

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TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346B – JANUARY 2007 – REVISED APRIL 2007

Table 3-29. Timer1 Block Function Selection

PINMUX1.TIM1BK

BLOCK FUNCTION

RESULTING PIN FUNCTIONS

GPIO (2) (default)

GPIO: GP[56:55]

Timer1

Timer1: TINP1L, TOUT1L

Reserved

–

Reserved

–

In addition, the VDD3P3V_PWDN.TIMER1 field determines the power state of the Timer1 Block pins. The

Timer1 Block pins default to powered down and not operational. To use these pins, user must first

program

VDD3P3V_PWDN.TIMER1

power

the

pins.

For

details

the

VDD3P3V_PWDN.TIMER1 field, see Section 3.2, Power Considerations.

The Timer1 Block features internal pull up resistors, which matches the UART inactive polarity.

3.7.3.8

Serial Port Block

This block of 12 pins consists of McASP0, McBSP0, and GPIO muxed pins. The following register fields

select the pin functions in the Serial Port Block:

• PINMUX1.SPBK0

• PINMUX1.SPBK1

The Serial Port Block is further subdivided into these sub-blocks:

• Serial Port Sub-Block 0: McBSP0, part of McASP0, and GPIO.

• Serial Port Sub-Block 1: part of McASP0 and GPIO.

Table 3-30 summarizes the 12 pins in the Serial Port Block, the multiplexed function on each pin, and the

PINMUX configurations to select the corresponding function.

Table 3-30. Serial Port Block Muxed Pins Selection

MULTIPLEXED FUNCTIONS

SIGNAL NAME

McASP0

McBSP0

GPIO

FUNCTION

SELECT

FUNCTION

SELECT

FUNCTION

SELECT

Serial Port Sub-block 0

ACLKR0/CLKX0/GP[99]

ACLKR0

CLKX0

GP[99]

AFSR0/DR0/GP[100]

AFSR0

DR0

GP[100]

AHCLKR0/CLKR0/GP[101]

AHCLKR0

CLKR0

GP[101]

SPBK0 = 10

SPBK0 = 01

SPBK0 = 00

AXR0[3]/FSR0/GP[102]

AXR0[3]

FSR0

GP[102]

AXR0[2]/FSX0/GP[103]

AXR0[2]

FSX0

GP[103]

AXR0[1]/DX0/GP[104]

AXR0[1]

DX0

GP[104]

Serial Port Sub-block 1

AXR0[0]/GP[105]

AXR0[0]

–

GP[105]

ACLKX0/GP[106]

ACLKX0

–

GP[106]

AFSX0/GP[107]

AFSX0

–

GP[107]

SPBK1 = 10

SPBK1 = 00

AHCLKX0/GP[108]

AHCLKX0

–

GP[108]

AMUTEIN0/GP[109]

AMUTEIN0

–

GP[109]

AMUTE0/GP[110]

AMUTE0

–

GP[110]

As discussed in Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks, the McBSP0 pins span

across two Pin Mux Blocks: Serial Port Sub-Block0, and Timer0 Block. For proper McBSP0 operation, the

Serial Port Sub-Block0 must be programmed to select McBSP0 function. The McBSP0 CLKS0 pin in the

Timer0 Block is optional for McBSP0 operation. CLKS0 is only needed if you desire using CLKS0 as an

external clock source to the McBSP0 internal sample rate generator.

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