TMS320C6421 datasheet(101/227 Pages) TI

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TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346B – JANUARY 2007 – REVISED APRIL 2007

In addition, the VDD3P3V_PWDN.PWM1 field determines the power state of the PWM1 Block pin. The

PWM1 Block pin defaults to powered down and not operational. To use this pin, user must first program

VDD3P3V_PWDN.PWM1 = 0 to power up the pin. For more details on the VDD3P3V_PWDN.PWM1 field,

see Section 3.2, Power Considerations.

3.7.3.10 CLKOUT Block

This block of 1 pin consists of CLKOUT, PWM2, and GPIO muxed pin (CLKOUT0/PWM2/GP[84]). The

PINMUX1.CKOBK register field selects the pin function in the CLKOUT Block.

Table 3-35 summarizes the 1 pin in the CLKOUT Block, its multiplexed function, and the PINMUX

configurations to select the corresponding function.

Table 3-35. CLKOUT Block Multiplexed Pin Selection

MULTIPLEXED FUNCTIONS

SIGNAL

CLKOUT0

PWM2

GPIO

NAME

FUNCTION

SELECT

FUNCTION

SELECT

FUNCTION

SELECT

CLKOUT0/

PWM2/

CLKOUT0

CKOBK = 01

PWM2

CKOBK = 10

GP[84]

CKOBK = 00

GP[84]

Table 3-36 provides a different view of the CLKOUT Block pin muxing, showing the CLKOUT Block

function based on PINMUX1.CKOBK setting. The selection options are also shown pictorially in

Figure 3-10.

Table 3-36. CLKOUT Block Function Selection

PINMUX1.CKOBK

BLOCK FUNCTION

RESULTING PIN FUNCTIONS

GPIO (1)

GPIO: GP[84]

CLKOUT (default)

Device Clock-Out: CLKOUT0

PWM2

PWM2: PWM2

Reserved

This block defaults to CLKOUT0 pin function.

In addition, the VDD3P3V_PWDN.CLKOUT field determines the power state of the CLKOUT Block pin.

The CLKOUT Block pin defaults to powered up. For more details on the VDD3P3V_PWDN.CLKOUT field,

see Section 3.2, Power Considerations.

3.7.3.11 EMIFA Block Muxing

This block of 61 pins consists of EMIFA, EMAC(RMII), and GPIO muxed pins. The following register fields

affect the pin functions in the EMIFA Block:

• All PINMUX0 register fields: AEM, CS5SEL, CS4SEL, CS3SEL, and RMII.

There is only one EMAC peripheral on the C6421 device, even though the pins for MII mode and the pins

for RMII modes are brought out to different locations. The EMAC MII mode pins are in the Host Block,

while EMAC RMII mode pins are only in the EMIFA Block. The user is only allowed to select either the MII

pins or the RMII pins. The operation is undefined if the user attempts to select both MII pins and RMII

pins.

The EMIFA Block is divided into multiple sub-blocks for ultimate flexibility in pin multiplexing to

accommodate a wide variety of applications, and for the purpose of I/O pins power control:

• Sub-Block 0: multiplexed between EMIFA address/control pins, part of EMAC(RMII), and GPIO.

• Sub-Block 1: multiplexed between EMIFA data/address/control pins, part of EMAC(RMII), and GPIO.

• Sub-Block 2: no multiplexing. EMIFA control pins EM_WAIT/(RDY/BSY), EM_OE, EM_WE.

• Sub-Block 3: multiplexed between EMIFA address pins EM_A[12:6] and GPIO.

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