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TMS320C6421 bảng dữ liệu(PDF) 93 Page - Texas Instruments |
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TMS320C6421 bảng dữ liệu(HTML) 93 Page - Texas Instruments |
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93 / 227 page  www.ti.com TMS320C6421 Fixed-Point Digital Signal Processor SPRS346B – JANUARY 2007 – REVISED APRIL 2007 Table 3-19. Multiplexed Pins on C6421 (continued) SIGNAL PINMUX DESCRIPTION ZWT ZDU NAME PINMUX GROUP CONTROLLED BY PINMUX BIT FIELDS NO. NO. HD11/MTXD3/GP[69] C5 A5 Host Block HOSTBK HD12/MTXD2/GP[70] D5 C5 Host Block HOSTBK HD13/MTXD1/GP[71] B4 B4 Host Block HOSTBK HD14/MTXD0/GP[72] D4 B5 Host Block HOSTBK HD15/MTXCLK/GP[73] A4 A4 Host Block HOSTBK HHWIL/MRXDV/GP[74] C4 D3 Host Block HOSTBK HCNTL1/MTXEN/GP[75] D3 C4 Host Block HOSTBK HCNTL0/MRXER/GP[76] B3 B2 Host Block HOSTBK HR/W/MRXCLK/GP[77] A3 A3 Host Block HOSTBK HDS2/MRXD0/GP[78] C3 C2 Host Block HOSTBK HDS1/MRXD1/GP[79] B2 B3 Host Block HOSTBK HRDY/MRXD2/GP[80] D2 C3 Host Block HOSTBK HCS/MDCLK/GP[81] C1 D1 Host Block HOSTBK HINT/MRXD3/GP[82] C2 D2 Host Block HOSTBK HAS/MDIO/GP[83] D1 C1 Host Block HOSTBK GP[4]/PWM1 F3 F3 PWM1Block PWM1BK ACLKR0/CLKX0/GP[99] H1 J1 Serial Port Sub-Block 0 SPBK0 AFSR0/DR0/GP[100] H4 K3 Serial Port Sub-Block 0 SPBK0 AHCLKR0/CLKR0/GP[101] J2 K1 Serial Port Sub-Block 0 SPBK0 AXR0[3]/FSR0/GP[102] G4 J3 Serial Port Sub-Block 0 SPBK0 AXR0[2]/FSX0/GP[103] H3 J2 Serial Port Sub-Block 0 SPBK0 AXR0[1]/DX0/GP[104] J3 K2 Serial Port Sub-Block 0 SPBK0 AXR0[0]/GP[105] H2 H2 Serial Port Sub-Block 1 SPBK1 ACLKX0/GP[106] F1 G1 Serial Port Sub-Block 1 SPBK1 AFSX0/GP[107] G2 G2 Serial Port Sub-Block 1 SPBK1 AHCLKX0/GP[108] G1 H1 Serial Port Sub-Block 1 SPBK1 AMUTEIN0/GP[109] F2 G3 Serial Port Sub-Block 1 SPBK1 AMUTE0/GP[110] G3 H3 Serial Port Sub-Block 1 SPBK1 TINP1L/GP[56] L4 P3 Timer 1 Block TIM1BK TOUT1L/GP[55] K4 N3 Timer 1 Block TIM1BK TINP0L/GP[98] K2 L2 Timer 0 Block TIM0BK CLKS0/TOUT0L/GP[97] J4 L3 Timer 0 Block TIM0BK URXD0/GP[85] L2 M2 UART0 Data Block UR0DBK UTXD0/GP[86] K3 N1 UART0 Data Block UR0DBK UCTS0/GP[87] L1 P1 UART0 Flow Control Block UR0FCBK URTS0/PWM0/GP[88] L3 M3 UART0 Flow Control Block UR0FCBK CLKOUT0/PWM2/GP[84] M1 R1 CLKOUT Block CKOBK Note: PINMUX group EMIFA Sub-Block 2 is not shown in the above table because there is no actual pin multiplexing in that block. However this block is still considered a "pin mux block" because it contains some of the pins necessary for EMIFA. The pins in this block are as follows: • EMIFA Sub-Block 2 – EM_WAIT/(RDY/BSY) – EM_OE – EM_WE Submit Documentation Feedback Device Configurations 93 |
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