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ANALOG FRONT END

PGA

(11 dB to –11 dB)

with MUX

G = –1

LIN+

R

R

R

R

R

MOUTL

LIN–

B0131−01

PCM1850A

PCM1851A

SLES173 – MARCH 2006

The PCM1850A/1851A has a built-in analog front-end circuit, which is shown in the block diagram of Figure 22.

Selection of the multiplexer input and PGA gain is controlled by mode control via the serial port as shown in

Table 2 and Table 3. The change of the input selection and the gain selection is performed immediately after the

serial control packet for the change is sent. A popping noise or other unexpected transient response could be

generated in the audio signal during channel and gain change. Because the PCM1850A/1851A has no

zero-cross detection and no other buffering capability for channel and gain change, appropriate data handling in

the digital domain is recommended to control transients.

The PCM1850A/1851A analog front end permits only ac input via an input capacitor; dc input is prohibited. A

signal source resistance of less than 1 k

Ω is recommended for the V

The PCM1850A/1851A employs MOUTL/R pins (pins 12 and 11) to monitor the multiplexer output. The load on

these pins must be ac-coupled and not less than 10 k

Ω. The full-scale output level is typically 0.6 V

Figure 22. Analog Front-End Block Diagram (L-Channel)

Table 2. Multiplexer Input Selection

CH2

CH1

CH0

CHANNEL

0

0

0

Mute

0

0

1

Channel 1 (default)

0

1

0

Channel 2

0

1

1

Channel 3

1

0

0

Channel 4

1

0

1

Channel 5

1

1

0

Channel 6

1

1

1

Mute

16

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