www.ti.com

Interface Timing

BCK

LRCK

DOUT

1.4 V

1.4 V

T0017-02

PCM1850A

PCM1851A

SLES173 – MARCH 2006

Figure 24 and Figure 25 illustrate the interface timing in slave and master modes, respectively.

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

BCK period

150

ns

BCK pulse duration, HIGH

60

ns

BCK pulse duration, LOW

60

ns

LRCK setup time to BCK rising edge

20

ns

LRCK hold time to BCK rising edge

20

ns

LRCK period

10

µs

Delay time, BCK falling edge to DOUT valid

–10

20

ns

Delay time, LRCK edge to DOUT valid

–10

20

ns

Rise time of all signals

10

ns

Fall time of all signals

10

ns

IN/OUT signal swing. Load capacitance of DOUT is 20 pF.

Figure 24. Audio Data Interface Timing (Slave Mode: LRCK, BCK Work as Inputs)

20

Submit Documentation Feedback