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SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM

NORMAL DATA

ZERO DATA

UNDEFINED

DATA

NORMAL DATA

SYNCHRONOUS

ASYNCHRONOUS

SYNCHRONOUS

Resynchronization

Synchronization Lost

DOUT

State of Synchronization

T0020-05

Power-Down Control

Overflow Flag Output

HPF Bypass Control

PCM1850A

PCM1851A

SLES173 – MARCH 2006

In slave mode, the PCM1850A/1851A operates under LRCK, synchronized with system clock SCKI. The

PCM1850A/1851A does not need a specific phase relationship between LRCK and SCKI, but does require the

synchronization of LRCK and SCKI.

If the relationship between LRCK and SCKI changes more than

±6 BCKs for 64 BCKs/frame (±5 BCKs for 48

and digital output is forced into the BPZ code until resynchronization between LRCK and SCKI is completed.

In the case of changes less than

±5 BCKs for 64 BCKs/frame (±4 BCKs for 48 BCKs/frame), resynchronization

with simultaneous discontinuity in the digital output does not occur.

Figure 26 illustrates the digital output response for loss of synchronization and resynchronization. During

undefined data, the PCM1850A/1851A might generate some noise in the audio signal. Also, the transition of

normal to undefined data and undefined or zero data to normal creates a discontinuity of data in the digital

output, which could generate some noise in the audio signal.

It is recommended to set RST (pin 10) to LOW to get stable analog performance when the sampling rate,

interface mode, or data format is changed.

Figure 26. ADC Digital Output for Loss of Synchronization and Resynchronization

RST (pin 10) controls the entire ADC operation. During reset mode, the supply current of the analog section is

shut off and the digital section is initialized. DOUT (pin 3) is also disabled. Halting SCKI, BCK, and LRCK is

recommended to minimize power dissipation.

RST

POWER-DOWN MODE

LOW

Reset and power-down modes

HIGH

Normal operation mode

The PCM1850A/1851A has an output flag (pin 4) that indicates when overflow occurs in the L-channel or

The built-in HPF function for dc component rejection can be bypassed via the serial port. In bypass mode, the dc

component of the analog input signal, the internal dc offset, etc., are converted and included in the digital output

data.

BYP

HPF (HIGH-PASS FILTER) MODE

0

Normal (no dc component on DOUT) mode (default)

1

Bypass (dc component on DOUT) mode

22

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