M750000004 datasheet(23/129 Pages) SPANSION

23 / 129 page

January 14, 2004

Am75PDL191CHHa/Am75PDL193CHHa

ADV ANCE

I N FO RMAT I O N

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re-

setting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of t

RP, the

device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was in-

terrupted should be reinitiated once the device is

ready to accept another command sequence, to en-

sure data integrity.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V

SS±0.3 V, the device

draws CMOS standby current (I

CC4). If RESET# is held

at V

IL but not within VSS±0.3 V, the standby current will

be greater.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

If RESET# is asserted during a program or erase op-

eration, the RY/BY# pin remains a “0” (busy) until the

internal reset operation is complete, which requires a

time of t

READY (during Embedded Algorithms). The sys-

tem can thus monitor RY/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

within a time of t

READY (not during Embedded Algo-

rithms). The system can read data t

RH after the RE-

SET# pin returns to V

IH.

Refer to the pSRAM AC Characteristics tables for RE-

SET# parameters and to Figure 15 for the timing dia-

gram.

Output Disable Mode

When the OE# input is at V

IH, output from the device is

disabled. The output pins (except for RY/BY#) are

placed in the highest Impedance state

Table 5.

SecSi

TM Sector Addresses

Sector Size

Address Range

Am29PDL127H/

Am29PDL129H

128 words

000000h–00007Fh

Factory-Locked Area

64 words

000000h-00003Fh

Customer-Lockable Area

64 words

000040h-00007Fh

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