M750000004 datasheet(22/129 Pages) SPANSION

22 / 129 page

Am75PDL191CHHa/Am75PDL193CHHa

January 14, 2004

ADV ANCE

I N FO RMAT I O N

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE#f1 or CE#f2 (PDL 129 only) to V

IL, and OE# to VIH.

The device features an Unlock Bypass mode to facili-

tate faster programming. Once a bank enters the Un-

lock Bypass mode, only two write cycles are required

to program a word, instead of four. The “Word Pro-

gram Command Sequence” section has details on

programming data to the device using both standard

and Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 4 indicates the address

space that each sector occupies. A “bank address” is

the address bits required to uniquely select a bank.

Similarly, a “sector address” refers to the address bits

required to uniquely select a sector. The “Command

Definitions” section has details on erasing a sector or

the entire chip, or suspending/resuming the erase op-

eration.

CC2 in the DC Characteristics table represents the ac-

tive current specification for the write mode. The AC

Characteristics section contains timing specification

tables and timing diagrams for write operations.

Accelerated Program Operation

The device offers accelerated program operations

through the ACC function. This function is primarily in-

tended to allow faster manufacturing throughput at the

factory.

If the system asserts V

HH on this pin, the device auto-

matically enters the aforementioned Unlock Bypass

mode, temporarily unprotects any protected sectors,

and uses the higher voltage on the pin to reduce the

time required for program operations. The system

would use a two-cycle program command sequence

as required by the Unlock Bypass mode. Removing

HH from the WP#/ACC pin returns the device to nor-

mal operation.

Note that VHH must not be asserted on

WP#/ACC for operations other than accelerated pro-

gramming, or device damage may result. In addition,

the WP#/ACC pin should be raised to VCC when not in

use. That is, the WP#/ACC pin should not be left float-

ing or unconnected; inconsistent behavior of the de-

vice may result.

Autoselect Functions

If the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ15–DQ0. Standard read cycle timings apply in

this mode. Refer to the Autoselect Command Se-

quence sections for more information.

Standby Mode

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

The device enters the CMOS standby mode when the

CE#f1, CE#f2 (PDL129 only) and RESET# pins are all

held at V

IO ± 0.3 V. (Note that this is a more restricted

voltage range than V

IH.) If CE#f1, CE#f2 (PDL129

only), and RESET# are held at V

IH, but not within VCC

± 0.3 V, the device will be in the standby mode, but the

standby current will be greater. The device requires

standard access time (t

CE) for read access when the

device is in either of these standby modes, before it is

ready to read data.

If the device is deselected during erasure or program-

ming , the device draws a ctive current until th e

operation is completed.

CC3 in the DC Characteristics table represents the

CMOS standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en-

ergy consumption. The device automatically enables

this mode when addresses remain stable for t

ACC +

150 ns. The automatic sleep mode is independent of

the CE#f1/CE#f2 (PDL129 only), WE#, and OE# con-

trol signals. Standard address access timings provide

new data when addresses are changed. While in

sleep mode, output data is latched and always avail-

able to the system. Note that during automatic sleep

mode, OE# must be at V

IH before the device reduces

current to the stated sleep mode specification. I

CC5 in

the DC Characteristics table represents the automatic

sleep mode current specification.

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