M750000004 datasheet(48/129 Pages) SPANSION

48 / 129 page

Am75PDL191CHHa/Am75PDL193CHHa

January 14, 2004

ADV ANCE

I N FO RMAT I O N

Once the SecSi Sector is locked and verified, the sys-

tem must write the Exit SecSi Sector Region com-

mand sequence to return to reading and writing the

remainder of the array.

The SecSi Sector lock must be used with caution

since, once locked, there is no procedure available for

unlocking the SecSi Sector area and none of the bits

in the SecSi Sector memory space can be modified in

any way.

SecSi Sector Protection Bits

The SecSi Sector Protection Bits prevent program-

ming of the SecSi Sector memory area. Once set, the

SecSi Sector memory area contents are non-modifi-

able.

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes. In addition, the following

hardware data protection measures prevent accidental

erasure or programming, which might otherwise be

caused by spurious system level signals during V

power-up and power-down transitions, or from system

noise.

Low VCC Write Inhibit

When V

CC is less than VLKO, the device does not ac-

cept any write cycles. This protects data during V

power-up and power-down. The command register

and all internal program/erase circuits are disabled,

and the device resets to the read mode. Subsequent

writes are ignored until V

CC is greater than VLKO. The

system must provide the proper signals to the control

pins to prevent unintentional writes when V

CC is

greater than V

LKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 3 ns (typical) on OE#,

CE#f1, CE#f2 or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

IL, CE#f1 =CE#f2 = VIH or WE# = VIH. To initiate a

write cycle, CE#f1/CE#f2 and WE# must be a logical

zero while OE# is a logical one.

Power-Up Write Inhibit

If WE# = CE#f1 = V

IL and OE# = VIH during power up,

the device does not accept commands on the rising

edge of WE#. The internal state machine is automati-

cally reset to the read mode on power-up.

COMMON FLASH MEMORY INTERFACE

(CFI)

The Common Flash Interface (CFI) specification out-

lines device and host system software interrogation

handshake, which allows specific vendor-specified

software algorithms to be used for entire families of

devices. Software support can then be device-inde-

pendent, JEDEC ID-independent, and forward- and

backward-compatible for the specified flash device

families. Flash vendors can standardize their existing

interfaces for long-term compatibility.

This device enters the CFI Query mode when the sys-

tem writes the CFI Query command, 98h, to address

55h, any time the device is ready to read array data.

The system can read CFI information at the addresses

given in Tables 12–15. To terminate reading CFI data,

the system must write the reset command. The CFI

Query mode is not accessible when the device is exe-

cuting an Embedded Program or embedded Erase al-

gorithm.

The system can also write the CFI query command

when the device is in the autoselect mode. The device

enters the CFI query mode, and the system can read

CFI data at the addresses given in Tables 12–15. The

system must write the reset command to return the

device to reading array data.

For further information, please refer to the CFI Specifi-

cation and CFI Publication 100, available via the World

Wide Web at http://www.amd.com/flash/cfi. Alterna-

tively, contact an AMD representative for copies of

these documents.

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