IRCC2.0 datasheet(76/87 Pages) SMSC

76 / 87 page

Burst Mode Receive

DRQ Control

In DMA Burst Mode, DRQ remains active until

the entire DMA data block has been transferred,

as indicated by DMA Terminal Count (TC).

Since the FIFO Threshold is not used for DMA

transfer cycles, DRQ is asserted as soon as

FIFO Not Empty is true.

FIFO Not Empty can

temporarily deactivate DRQ if the DMA block has

not been completely transferred but there is no

data left in the FIFO to transfer.

As soon as

FIFO

Not

Empty

becomes

true,

DRQ

reasserted.

The internal refresh counter can

also temporarily deactivate DRQ (see the DMA

Refresh Counter on page 74).

Example: Receive a 256-Byte IrDA Message

Setup and enable the DMA controller for the

256-byte message.

Enable the IrDA Receiver.

DRQ is asserted as soon as FIFO Not

Empty is true.

The DMA controller proceeds to empty the

FIFO until TC. DRQ is otherwise only de-

asserted when FIFO Not Empty is false or

Refresh Interval is active (Figure 42).

DMA Enable

DRQ

FIFO FULL

DMA Burst

Refresh Interval

Tx Enable

TxServReq

FIGURE 41 - DMA BURST MODE TRANSMIT TIMING

DMA Enable

DRQ

FIFO NOT EMPTY

DMA Burst

Refresh Interval

Rx Enable

FIGURE 42 - DMA BURST MODE RECEIVE TIMING

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