IRCC2.0 datasheet(35/87 Pages) SMSC

35 / 87 page

No Wait, bit 3

When the No Wait bit is one, the ISA Bus

nSRDY signal goes active following the trailing

edge of the ISA I/O command and inactive

following the rising edge (see the Zero Wait State

Support section on page 80).

String Move, Bit 2

When

the

String

Move

bit

one,

the

programmed I/O host interface is qualified by

IOCHRDY (Table 23). See the IOCHRDY Time-

Out section on page 79.

DMA Burst Mode, bit 1

When the DMA Burst Mode bit is one, DMA

Burst (Demand) mode is enabled.

When the

DMA Burst Mode bit is zero, Single Byte DMA

mode is enabled (Table 23). See the DMA

section on page 73.

DMA Enable, bit 0

DMA Enable is connected to a signal in the

Interface Description called DMAEN that is used

by the chip-level interface to tristate the IrCC 2.0

DMA

controls

when

the

DMA interface

inactive. When the DMA Enable bit is one, the

DMA host interface is active (Table 23). See the

DMA section on page 73.

When the DMA

Enable bit is zero (default), the nDACK and TC

inputs are disabled and DRQ output is gated off.

Table 23 - I/O Interface Modes

STRING

MOVE

DMA

BURST

DMA

ENABLE

FUNCTION

Programmed I/O, no IOCHRDY

Programmed I/O, uses IOCHRDY

Single Byte DMA Mode

Demand Mode DMA

FIFO Threshold Register (Address 2)

The FIFO Threshold Register contains the

programmable FIFO threshold count (see the

FIFO Threshold section on page 72). The FIFO

Threshold is programmable from 0 to 127. Bit 7

in the FIFO Threshold register is read-only and

will always return zero. FIFO Threshold values

typically reflect the overall I/O performance

characteristics of the host; the lower the value,

the longer the interval between service requests

and the faster the host must be to successfully

service them. The same threshold value can be

used for both I/O read and I/O write cases.

FIFO COUNT Register (Address 3)

The

FIFO

COUNT

represents

the

remaining number of data bytes in the 128-byte

SCE FIFO. When the FIFO COUNT is 0x00 the

FIFO is empty. When the FIFO is full the FIFO

COUNT

0x80.

The

FIFO

COUNT

independent of the data flow direction.

For

example, if the FIFO COUNT is 0x0A during

transmit there are ten bytes to send; if the FIFO

COUNT is 0x0A during receive there are ten

bytes to read.

Message Byte Count Registers (Address 4

and 5)

The Message Byte Count registers are used to

program, retain and retrieve the number of Tx

and Rx message bytes in IrDA multi-frame

windows (see the Multi-Frame Window Support

section on page 67). The eight 12-bit Message

Byte Count registers are accessed through two

consecutive 8 bit registers at address 0x04 and

address 0x05. Access to any of these eight

registers is controlled by the write-only Line

Status Address Register at address 0x03 in

mechanism that controls access to the eight line

status registers. The actual byte count per

received message depends upon the value

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