AD9949

Rev. B | Page 20 of 36

NOTES

1. DIGITAL OUTPUT DATA (DOUT) PHASE IS ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.

2. WITHIN ONE CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO ANY OF THE 48 LOCATIONS.

P[0]

P[48] = P[0]

CLI

1 PIXEL PERIOD

P[12]

P[24]

P[36]

DOUT

Figure 19. Digital Output Phase Adjustment

NOTES

1. DEFAULT TIMING VALUES ARE SHOWN: SHDLOC = 0, DOUT PHASE = 0.

2. HIGHER VALUES OF SHD AND/OR DOUTPHASE WILL SHIFT DOUT TRANSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION.

DOUT

CCDIN

CLI

SHD

(INTERNAL)

N

N + 1

N + 2

N + 12

N + 11

N + 10

N + 9

N + 8

N + 7

N + 6

N + 5

N + 4

N + 3

N + 13

N – 13

N– 3

N– 4

N– 5

N– 6

N– 7

N– 8

N– 9

N – 10

N – 11

N – 12

N– 2

N– 1

N + 1

N

SAMPLE PIXEL N

N– 1

PIPELINE LATENCY = 11 CYCLES

Figure 20. Pipeline Delay for Digital Data Output