L160DB90VC datasheet(12/52 Pages) AMD

12 / 52 page

Am29LV160D

May 5, 2006 22358B7

DA TA

SH EET

sectors of memory), the system must drive WE# and

CE# to VIL, and OE# to VIH.

For program operations, the BYTE# pin determines

whether the device accepts program data in bytes or

words. Refer to “Word/Byte Configuration” for more

information.

The device features an Unlock Bypass mode to facili-

tate faster programming. Once the device enters the

Unlock Bypass mode, only two write cycles are re-

quired to program a word or byte, instead of four. The

“Word/Byte Program Command Sequence” section

has details on programming data to the device using

both standard and Unloc k Bypas s command

sequences.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Tables 2 and 3 indicate the

address space that each sector occupies. A “sector

address” consists of the address bits required to

uniquely select a sector. The “Command Definitions”

section has details on erasing a sector or the entire

chip, or suspending/resuming the erase operation.

After the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in

this mode. Refer to the “Autoselect Mode” and “Au-

toselect Command Sequence” sections for more

information.

ICC2 in the DC Characteristics table represents the ac-

tive current specification for the write mode. The “AC

Characteristics” section contains timing specification

tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system

may check the status of the operation by reading the

status bits on DQ7–DQ0. Standard read cycle timings

and ICC read specifications apply. Refer to “Write Op-

eration Status” for more information, and to “AC

Characteristics” for timing diagrams.

Standby Mode

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at VCC ± 0.3 V.

(Note that this is a more restricted voltage range than

VIH.) If CE# and RESET# are held at VIH, but not

within VCC ± 0.3 V, the device will be in the standby

mode, but the standby current will be greater. The de-

vice requires standard access time (tCE) for read

access when the device is in either of these standby

modes, before it is ready to read data.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

In the DC Characteristics table, ICC3 and ICC4 repre-

sents the standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device

energy consumption. The device automatically

enables this mode when addresses remain stable for

t AC C + 3 0 ns. The a u tomati c sle ep mo de is

independent of the CE#, WE#, and OE# control

signals. Standard address access timings provide new

data when addresses are changed. While in sleep

mode, output data is latched and always available to

the system. ICC4 in the DC Characteristics table

repr esen ts th e automatic sleep mo de cu rren t

specification.

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