TPS25751D datasheet(72/89 Pages) TI1

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5A of current. When connecting the PP_EXT plane to a different layer, use a minimum of 6 vias in parallel per

layer change. It is highly recommended to have more than 6 vias if possible for layer change to improve current

sharing and efficiency.

VSYS (pin 19)

The VSYS pin (pin 19) can be connected with a trace (recommended 6mil trace width) to any of the vias on the

PPHV plane. It is recommended to connect to a via close to the source pin of the VSYS N-ch MOSFET(pins A2,

B2, D2, and E2 of the Q1 FET in the example schematic) to improve reverse current sensing protection. Refer to

section 9.3.3.2.2 for additional information on RCP.

9.4.2.2.2.4 TPS25751S VBUS

VBUS (pins 26 and 27)

Place the VBUS decoupling capacitor (C1) as close as possible to TPS25751S, the capacitor does not need to

be on the same layer as the device. The VBUS power plane need to be sized to support up to 5A of current

if 100W application is required. When connecting the VBUS pins (pins 26 and 27) plane to a different layer,

use a minimum of 3 vias per layer change. When connecting the VBUS power plane to a different layer, use a

minimum of 6 vias per layer change. Refer to figure 10-21 and figure 10-22 for capacitors and via placement.

At the Type-C port/connector, it is recommended to use minimum of 6 vias from the connector VBUS pins for

layer changes. Place the 10nF caps (C2, C3, C4, and C5) and the 22V TVS diode (U2) as close as possible to

the connector VBUS pins as shown in figure 10-22.

When routing the VBUS power plane from the Type-C connector to the TPS25751S VBUS pins, minimize bottle

necks caused by other vias and traces to improve current flow. The example layout shown in figure 10-24 uses

an internal layer to route the VBUS plane from the connector to TPS25751S.

9.4.2.2.2.5 TPS25751S I/O

I2C, ADCIN1/2, and GPIO pins

Fan these traces out from the TPS25751S, use vias to connect the net to a routing layer if needed. For these

nets, use 4mil to 10mil trace width.

I2Cc_SDA/SCL/IRQ (pins 8, 9, and 10) and I2Ct_SCL/SDA/IRQ (pins 15, 16, and 17)

Minimize trace width changes to avoid I2C communication issues.

ADCIN1 and ADCIN2 (pins 2 and 3)

Keep the ADCINx traces away from switching elements. If a resistor divider is used, place the divider close to

LDO_3V3 or LDO_1V5.

GPIO (pins 5, 6, 7, 18, 22, 23, 31, 30, and 13)

Separate GPIO traces running in parallel by a trace width. Keep the GPIOx traces away from switching

elements.

9.4.2.2.2.6 TPS25751S PPEXT Gate Driver

GATE_VSYS (pin 20)

The GATE_VSYS pin (pin 20) can be connected with a trace (recommended 6mil trace width) to the gate pins of

the N-ch MOSFET with source tied to PPHV. It is recommended to NOT via directly to the gate pin of the N-ch

MOSFET, instead use via(s) to connect the GATE_VSYS pin from the TPS25751S to the gate pin of the N-ch

MOSFET. Refer to figure 10-21 and figure 10-22 for examples on how to connect the traces.

GATE_VBUS (pin 21)

The GATE_VBUS pin (pin 21) can be connected with a trace (recommended 6mil trace width) to the gate pins of

the N-ch MOSFET with source tied to VBUS. It is recommended to NOT via directly to the gate pin of the N-ch

MOSFET, instead use via(s) to connect the GATE_VBUS pin from the TPS25751S to the gate pin of the N-ch

MOSFET. Refer to figure 10-21 and figure 10-22 for examples on how to connect the traces.

TPS25751

SLVSH93 – OCTOBER 2023

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