NRF51802-QFAA-R datasheet(16/85 Pages) NORDIC

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Page 16

nRF51802 Product Specification v1.2

3.2

Memory

All memory and registers are found in the same address space as shown in the Device Memory Map, see

Figure 4. Devices in the nRF51 series use flash based memory in the code, FICR, and UICR regions.

The RAM region is SRAM.

Figure 4 Memory Map

The embedded flash memory for program and static data can be programmed using In Application

Programming (IAP) routines from RAM through the SWD interface, or in-system from a program executing

from code area. The Non-Volatile Memory Controller (NVMC) is used for program/erase operations. Regions

of flash memory can be protected from read, write, and erase by the Memory Protection Unit (MPU). A User

Information Configuration Register (UICR) contains the lock byte for enabling readback protection to secure

the IP, while individual block protection is controlled using registers which can only be cleared on chip reset.

reserved

0xFFFFFFFF

Private Peripheral Bus

0xE0100000

reserved

AHB peripherals

0xE0000000

0x50000000

APB peripherals

reserved

RAM

0x40000000

0x20000000

reserved

FICR

reserved

Code

0x00000000

0x10000000

0x40080000

UICR

reserved

0x10001000

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