NRF51802-QFAA-R datasheet(44/85 Pages) NORDIC

tên linh kiện	NRF51802-QFAA-R

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Page 44

nRF51802 Product Specification v1.2

8.3

Block resource requirements

Table 31 Clock and power requirements for different blocks

8.4

CPU

Table 32 CPU specifications

Block

Resource requirements

Comment

1V2

HFCLK1

1. HFCLK could be one of the following; RC16M, XO16M, or XO32M.

LFCLK

1V7

Radio

Requires HFCLK XOSC.

UART

When receiver or transmitter are

STARTed.

SPIS

Requested when CSN asserts.

SPI

3, 4

TWI

3, 4

GPIOTE

Only in input mode.

ADC

Requires HFCLK XOSC.

TIMER

8, 9, 10

Requires 1V2 when a TIMER EVENT is

triggered.

RTC

11, 17

HFCLK will be requested if the LFCLK is

synthesized from HFCLK.

TEMP

Requires HFCLK XOSC.

RNG

ECB

WDT

HFCLK will be requested if the LFCLK is

synthesized from HFCLK.

QDEC

LPCOMP

No resources required.

CPU

Symbol

Description

Min.

Typ.

Max.

Units

Test

level

ICPU, FLASH

Run current at 16 MHz (XOSC).

Executing code from flash memory.

4.11

1. Includes CPU, flash, 1V2, 1V7, RC16M.

ICPU, RAM

Run current at 16 MHz (XOSC).

Executing code from RAM.

2.42

2. Includes CPU, RAM, 1V2, RC16M.

ISTART, CPU

CPU startup current.

600

μA

tSTART, CPU

IDLE to CPU execute.

3.53

3. t1V2 must be added if the 1V2 regulator is not running already.

μs

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