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UJA1069 bảng dữ liệu(PDF) 57 Page - NXP Semiconductors |
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UJA1069 bảng dữ liệu(HTML) 57 Page - NXP Semiconductors |
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57 / 64 page ![]() UJA1069_2 © NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 02 — 5 March 2007 57 of 64 NXP Semiconductors UJA1069 LIN fail-safe system basis chip 11. Test information Immunity against automotive transients (malfunction and damage) in accordance with LIN EMC Test Specification / Version 1.0; August 1, 2004. 11.1 Quality information This product has been qualified to the appropriate Automotive Electronics Council (AEC) standard Q100 or Q101 and is suitable for use in automotive critical applications. Fig 25. Timing test circuit for LIN transceiver 001aad179 SBC BAT42 GND LIN RTLIN TXDL R1 20 pF R2 C1 RXDL Fig 26. Timing diagram LIN transceiver 001aaa346 VTXDL LIN BUS signal receiving node 1 receiving node 2 VBAT42 VRXDL1 VRXDL2 tbit tbus(dom)(max) tbus(rec)(min) Vth(reces)(max) thresholds of receiving node 1 Vth(dom)(max) Vth(reces)(min) Vth(dom)(min) tbus(dom)(min) tp(rx)r tp(rx)f tp(rx)r tp(rx)f tbus(rec)(max) tbit tbit thresholds of receiving node 2 |
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