AT87C5103-ICSIL datasheet(48/64 Pages) ATMEL

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AT8xC5103

4134C–8051–09/04

Table 31. IE0 Register

IE0 (S:A8h)

Interrupt Enable Register

Reset Value = 00XX 0000b

Bit addressable

543

210

ET1

EX1

ET0

EX0

Bit

Number

Bit

Mnemonic

Description

7EA

Enable All Interrupt Bit

Clear to disable all interrupts.

Set to enable all interrupts.

If EA=1, each interrupt source is individually enabled or disabled by setting or

clearing its interrupt enable bit.

6EC

PCA Interrupt Enable

Clear to disable the PCA interrupt.

Set to enable the PCA interrupt.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

3ET1

Timer 1 overflow interrupt Enable bit

Clear to disable timer 1 overflow interrupt.

Set to enable timer 1 overflow interrupt.

EX1

External Interrupt 1 Enable bit

Clear to disable external interrupt 0.

Set to enable external interrupt 0.

1ET0

Timer 0 Overflow Interrupt Enable bit

Clear to disable timer 0 overflow interrupt.

Set to enable timer 0 overflow interrupt.

EX0

External Interrupt 0 Enable bit

Clear to disable external interrupt 0.

Set to enable external interrupt 0.

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