AT87C5103-ICSIL datasheet(30/64 Pages) ATMEL

30 / 64 page

AT8xC5103

4134C–8051–09/04

Mode 0 (13-bit Timer)

Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 reg-

ister) with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 register

(see Figure 15). The upper 3 bits of TL1 register are ignored. Prescaler overflow incre-

ments TH1 register.

Mode 1 (16-bit Timer)

Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connected in

cascade (see Figure 16). The selected input increments TL1 register.

Mode 2 (8-bit Timer with Auto-

Reload)

Mode 2 configures Timer 1 as an 8-bit Timer (TL1 register) with automatic reload from

TH1 register on overflow (see Figure 17). TL1 overflow sets TF1 flag in TCON register

and reloads TL1 with the contents of TH1, which is preset by software. The reload

leaves TH1 unchanged.

Mode 3 (Halt)

Placing Timer 1 in Mode 3 causes it to halt and hold its count. This can be used to halt

Timer 1 when TR1 run control bit is not available i.e. when Timer 0 is in Mode 3.

Interrupt

Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This

flag is set every time an overflow occurs. Flags are cleared when vectoring to the Timer

interrupt routine. Interrupts are enabled by setting ETx bit in IE0 register. This assumes

interrupts are globally enabled by setting EA bit in IE0 register.

Figure 19. Timer Interrupt System

TF0

TCON.5

ET0

IE0.1

Timer 0

Interrupt Request

TF1

TCON.7

ET1

IE0.3

Timer 1

Interrupt Request

AT87C5103-ICSIL bảng dữ liệu(PDF) 30 Page - ATMEL Corporation