AT83SND1CXXX-ROTIL datasheet(149/212 Pages) ATMEL

149 / 212 page

149

4109J–8051–10/06

AT8xC51SND1C

For simplicity, Figure 18-5 and Figure 18-6 depict the SPI waveforms in idealized form and do

not provide precise timing information. For timing parameters refer to the Section “AC

Characteristics”.

Note:

1. When the peripheral is disabled (SPEN = 0), default SCK line is high level.

Figure 18-5. Data Transmission Format (CPHA = 0)

Figure 18-6. Data Transmission Format (CPHA = 1)

18.1.5

SS Management

Figure 18-5 shows an SPI transmission with CPHA = 0, where the first SCK edge is the MSB

capture point. Therefore the slave starts to output its MSB as soon as it is selected: SS asserted

to low level. SS must then be deasserted between each Byte transmission (see Figure 18-7).

SPDAT must be loaded with a data before SS is asserted again.

Figure 18-6 shows an SPI transmission with CPHA = 1, where the first SCK edge is used by the

slave as a start of transmission signal. Therefore, SS may remain asserted between each Byte

transmission (see Figure 18-7).

MSB

bit 1

LSB

bit 2

bit 4

bit 3

bit 6

bit 5

bit 1

bit 2

bit 4

bit 3

bit 6

bit 5

MSB

LSB

MOSI (From Master)

MISO (From Slave)

SCK (CPOL = 1)

SCK (CPOL = 0)

SPEN (Internal)

SCK Cycle Number

SS (to slave)

Capture point

MSB

bit 1

LSB

bit 2

bit 4

bit 3

bit 6

bit 5

bit 1

bit 2

bit 4

bit 3

bit 6

bit 5

MSB

LSB

MOSI (from master)

MISO (from slave)

SCK (CPOL = 1)

SCK (CPOL = 0)

SPEN (internal)

SCK cycle number

SS (to slave)

Capture point

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