AT83SND1CXXX-ROTIL datasheet(148/212 Pages) ATMEL

148 / 212 page

148

4109J–8051–10/06

AT8xC51SND1C

When the AT8xC51SND1C is the only slave on the bus, it can be useful not to use SS pin and

get it back to I/O functionality. This is achieved by setting SSDIS bit in SPCON. This bit has no

effect when CPHA is cleared (see Section "SS Management", page 149).

Figure 18-4. SPI Slave Mode Block Diagram

Note:

1. MSTR bit in SPCON is cleared to select slave mode.

18.1.3

Bit Rate

The bit rate can be selected from seven predefined bit rates using the SPR2, SPR1 and SPR0

control bits in SPCON according to Table 121. These bit rates are derived from the peripheral

clock (F

PER) issued from the Clock Controller block as detailed in Section "Oscillator", page 12.

Table 121. Serial Bit Rates

Notes:

1. These frequencies are achieved in X1 mode, F

PER = FOSC ÷ 2.

2. These frequencies are achieved in X2 mode, FPER = FOSC.

18.1.4

Data Transfer

The Clock Polarity bit (CPOL in SPCON) defines the default SCK line level in idle state(1) while

the Clock Phase bit (CPHA in SPCON) defines the edges on which the input data are sampled

and the edges on which the output data are shifted (see Figure 18-5 and Figure 18-6). The SI

signal is output from the selected slave and the SO signal is the output from the master. The

AT8xC51SND1C captures data from the SI line while the selected slave captures data from the

SO line.

MISO/P4.2

MOSI/P4.1

SS/P4.3

SPIF

SPSTA.7

CPOL

SPCON.3

CPHA

SPCON.2

8-bit Shift Register

SPDAT WR

SPDAT RD

SCK/P4.2

SSDIS

SPCON.5

Control and Clock Logic

SPR2

SPR1

SPR0

Bit Rate (kHz) Vs FPER

FPER Divider

6 MHz

(1)

8 MHz

(1)

10 MHz

(1)

12 MHz

(2)

16 MHz

(2)

20 MHz

(2)

3000

4000

5000

6000

8000

10000

1500

2000

2500

3000

4000

5000

750

1000

1250

1500

2000

2500

375

500

625

750

1000

1250

187.5

250

312.5

375

500

625

93.75

125

156.25

187.5

250

312.5

46.875

62.5

78.125

93.75

125

156.25

128

6000

8000

10000

12000

16000

20000

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