AT83SND1CXXX-ROTIL datasheet(127/212 Pages) ATMEL

127 / 212 page

127

4109J–8051–10/06

AT8xC51SND1C

Reset Value = 0000 0011b

15.8.0.5

Table 107. MMMSK Register

MMMSK (S:DFh) – MMC Interrupt Mask Register

6EORI

End of Response Interrupt Flag

Set by hardware at the end of response reception.

Cleared when reading MMINT.

5EOCI

End of Command Interrupt Flag

Set by hardware at the end of command transmission.

Clear when reading MMINT.

4EOFI

End of Frame Interrupt Flag

Set by hardware at the end of frame (stream or block) transfer.

Clear when reading MMINT.

3F2FI

FIFO 2 Full Interrupt Flag

Set by hardware when second FIFO becomes full.

Cleared by hardware when second FIFO becomes empty.

2F1FI

FIFO 1 Full Interrupt Flag

Set by hardware when first FIFO becomes full.

Cleared by hardware when first FIFO becomes empty.

1F2EI

FIFO 2 Empty Interrupt Flag

Set by hardware when second FIFO becomes empty.

Cleared by hardware when second FIFO becomes full.

0F1EI

FIFO 1 Empty Interrupt Flag

Set by hardware when first FIFO becomes empty.

Cleared by hardware when first FIFO becomes full.

Bit

Number

Bit

Mnemonic

Description

7654

3210

MCBM

EORM

EOCM

EOFM

F2FM

F1FM

F2EM

F1EM

Bit

Number

Bit

Mnemonic

Description

7MCBM

MMC Card Busy Interrupt Mask Bit

Set to prevent MCBI flag from generating an MMC interrupt.

Clear to allow MCBI flag to generate an MMC interrupt.

6EORM

End Of Response Interrupt Mask Bit

Set to prevent EORI flag from generating an MMC interrupt.

Clear to allow EORI flag to generate an MMC interrupt.

5EOCM

End Of Command Interrupt Mask Bit

Set to prevent EOCI flag from generating an MMC interrupt.

Clear to allow EOCI flag to generate an MMC interrupt.

4EOFM

End Of Frame Interrupt Mask Bit

Set to prevent EOFI flag from generating an MMC interrupt.

Clear to allow EOFI flag to generate an MMC interrupt.

3F2FM

FIFO 2 Full Interrupt Mask Bit

Set to prevent F2FI flag from generating an MMC interrupt.

Clear to allow F2FI flag to generate an MMC interrupt.

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