AT83SND1CXXX-ROTIL datasheet(125/212 Pages) ATMEL

125 / 212 page

125

4109J–8051–10/06

AT8xC51SND1C

15.8.0.2

Table 104. MMCON2 Register

MMCON2 (S:E6h) – MMC Control Register 2

Reset Value = 0000 0000b

15.8.0.3

Table 105. MMSTA Register

MMSTA (S:DEh Read Only) – MMC Control and Status Register

7654

3210

MMCEN

DCR

CCR

DATD1

DATD0

FLOWC

Bit

Number

Bit

Mnemonic

Description

7MMCEN

MMC Clock Enable Bit

Set to enable the MCLK clocks and activate the MMC controller.

Clear to disable the MMC clocks and freeze the MMC controller.

6DCR

Data Controller Reset Bit

Set and clear to reset the data line controller in case of transfer abort.

5CCR

Command Controller Reset Bit

Set and clear to reset the command line controller in case of transfer abort.

4-3

Reserved

The value read from these bits is always 0. Do not set these bits.

2-1

DATD1:0

Data Transmission Delay Bits

Used to delay the data transmission after a response from 3 MMC clock periods

(all bits cleared) to 9 MMC clock periods (all bits set) by step of 2 MMC clock

periods.

0FLOWC

MMC Flow Control Bit

Set to enable the flow control during data transfers.

Clear to disable the flow control during data transfers.

7654

3210

CBUSY

CRC16S

DATFS

CRC7S

RESPFS

CFLCK

Bit

Number

Bit

Mnemonic

Description

7 - 6

Reserved

The value read from these bits is always 0. Do not set these bits.

5CBUSY

Card Busy Flag

Set by hardware when the card sends a busy state on the data line.

Cleared by hardware when the card no more sends a busy state on the data line.

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