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AT83SND1CXXX-ROTIL bảng dữ liệu(PDF) 126 Page - ATMEL Corporation |
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AT83SND1CXXX-ROTIL bảng dữ liệu(HTML) 126 Page - ATMEL Corporation |
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126 / 212 page  126 4109J–8051–10/06 AT8xC51SND1C Reset Value = 0000 0000b 15.8.0.4 Table 106. MMINT Register MMINT (S:E7h Read Only) – MMC Interrupt Register 4 CRC16S CRC16 Status Bit Transmission mode Set by hardware when the token response reports a good CRC. Cleared by hardware when the token response reports a bad CRC. Reception mode Set by hardware when the CRC16 received in the data block is correct. Cleared by hardware when the CRC16 received in the data block is not correct. 3 DATFS Data Format Status Bit Transmission mode Set by hardware when the format of the token response is correct. Cleared by hardware when the format of the token response is not correct. Reception mode Set by hardware when the format of the frame is correct. Cleared by hardware when the format of the frame is not correct. 2 CRC7S CRC7 Status Bit Set by hardware when the CRC7 computed in the response is correct. Cleared by hardware when the CRC7 computed in the response is not correct. This bit is not relevant when CRCDIS is set. 1 RESPFS Response Format Status Bit Set by hardware when the format of a response is correct. Cleared by hardware when the format of a response is not correct. 0CFLCK Command FIFO Lock Bit Set by hardware to signal user not to write in the transmit command FIFO: busy state. Cleared by hardware to signal user the transmit command FIFO is available: idle state. Bit Number Bit Mnemonic Description 7654 3210 MCBI EORI EOCI EOFI F2FI F1FI F2EI F1EI Bit Number Bit Mnemonic Description 7MCBI MMC Card Busy Interrupt Flag Set by hardware when the card enters or exits its busy state (when the busy signal is asserted or deasserted on the data line). Cleared when reading MMINT. |
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