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WM8581 bảng dữ liệu(PDF) 86 Page - Wolfson Microelectronics plc |
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WM8581 bảng dữ liệu(HTML) 86 Page - Wolfson Microelectronics plc |
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86 / 100 page  WM8581 Production Data w PD Rev 4.0 April 2007 86 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 7:0 RDA3[7:0] 11111111 (0dB) Digital Attenuation control for DAC3 Right Channel (DACR3) in 0.5dB steps. See Table 23 R25 DIGITAL ATTENUATION DACR 3 19h 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0 = Store RDA3 in intermediate latch (no change to output) 1 = Apply RDA3 and update attenuation on all channels 7:0 LDA4[7:0] 11111111 (0dB) Digital Attenuation control for DAC4 Left Channel (DACL4) in 0.5dB steps. See Table 23 R26 DIGITAL ATTENUATION DACL 4 1Ah 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0 = Store LDA4 in intermediate latch (no change to output) 1 = Apply LDA4 and update attenuation on all channels 7:0 RDA4[7:0] 11111111 (0dB) Digital Attenuation control for DAC4 Right Channel (DACR4) in 0.5dB steps. See Table 23 R27 DIGITAL ATTENUATION DACR 4 1Bh 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0 = Store RDA4 in intermediate latch (no change to output) 1 = Apply RDA4 and update attenuation on all channels 7:0 MASTDA[7:0] 11111111 (0dB) Digital Attenuation control for all DAC channels in 0.5dB steps. See Table 23 R28 MASTER DIGITAL ATTENUATION 1Ch 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0 = Store gain in intermediate latch (no change to output) 1 = Apply gain and update attenuation on all channels 0 AMUTEL 0 ADC Mute select 0 : Normal Operation 1: mute ADC left 1 AMUTER 0 ADC Mute select 0 : Normal Operation 1: mute ADC right 2 AMUTEALL 0 ADC Mute select 0 : Normal Operation 1: mute both ADC channels 3 ADCOSR 0 ADC oversample rate select 0 = 128/64 x oversampling 1 = 64/32 x oversampling 4 ADCHPD 0 ADC high-pass filter disable: 0 = high-pass filter enabled 1 = high-pass filter disabled 7:5 ADCRATE[2:0] 010 ADC Rate Control (only used when the S/PDIF Transmitter is the only interface sourcing the ADC) 000 = 128fs 001 = 192fs 010 = 256fs 011 = 384fs 100 = 512fs 101 = 768fs 110 = 1152fs R29 ADC CONTROL 1 1Dh 8 VMIDSEL 1 VMID Impedance Selection 0 = High impedance, power saving 1 = Low impedance, fast power-on R30 SPDTXCHAN 0 1Eh 1:0 TXSRC[1:0] 10 S/PDIF Transmitter Data Source 00 = S/PDIF received data (see REAL_THROUGH) 01 = ADC digital output data. 10 = Secondary Audio Interface 11 = Audio Interface received data |
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