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WM8581 bảng dữ liệu(PDF) 46 Page - Wolfson Microelectronics plc

tên linh kiện WM8581
Giải thích chi tiết về linh kiện  Multichannel CODEC with S/PDIF Transceiver
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nhà sản xuất  WOLFSON [Wolfson Microelectronics plc]
Trang chủ  http://www.wolfsonmicro.com
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WM8581 bảng dữ liệu(HTML) 46 Page - Wolfson Microelectronics plc

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WM8581
Production Data
w
PD Rev 4.0 April 2007
46
PRIMARY AUDIO INTERFACE RECEIVER (PAIF RX)
The PAIF Receiver requires a left-right-clock (LRCLK) and a bit-clock (BCLK). These can be supplied
externally (slave mode) or they can be generated internally by the WM8581 (master mode). The
master mode LRCLK/BCLK are created by the Master Mode Clock Gen module. The control of this
module is described on page 34. The clock supplied to this module is selected by the
PAIFRXMS_CLKSEL register and can be MCLK, PLLACLK, or PLLBCLK.
Figure 29 PAIF Receiver Clock Selection
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R9
7:6
PAIFRXMS_
CLKSEL
00
PAIFRX Master Mode clock source
00 = MCLK pin
01 = PLLACLK
10 = PLLBCLK
11 = MCLK pin
Table 36 PAIF Receiver Master Mode Clock Control



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