AD9549 datasheet(28/78 Pages) AD

28 / 78 page

AD9549

Preliminary Technical Data

Rev. PrA | Page 28 of 78

The phase gain of the fine phase detector is controlled by an 8-

bit scale factor (FPFD_Gain) in the I/O Register Map. The

nominal (default) value of FPFD_Gain is 200, and establishes

the phase gain as:

(

)()

Gain

FPFD

FPD

PhaseGain

Phase Detector Gain Matching

Although the fine and coarse phase detectors use different

means to make a timing measurement, it is essential that both

have equivalent phase gain. Without proper gain matching the

closed-loop dynamics of the system cannot be properly

controlled. Hence, the goal is to make PhaseGainCPD=

PhaseGainFPD. This leads to:

(

)

(

)

Gain

FPFD

PDG

PDS

Which simplifies to:

(

)

Gain

FPFD

PDS PDG

⋅

Typically, FPFD_Gain is established first and then PDG and

PDS are calculated. The proper choice for PDS is given by:

(

)

[

]

Gain

FPFD

round

PDS

log

The final value of PDS must satisfy 0 ≤ PDS ≤ 7. The proper

choice for PDG is calculated using this equation:

(

)

PDS

Gain

FPFD

round

PDG

−

The final value of PDG must satisfy 0 ≤ PDG ≤ 63. For

example, let fS=700MHz and FPFD_Gain=200, then PDS=1 and

PDG=23.

Note that the AD9549 Evaluation Software will calculate

matched.

Phase Detector Pin Connections

There are three pins associated with the phase detector that

must be connected to external components. The diagram below

shows the recommended component values and their

connections.

PFD_VRB

PFD_VRT

PFD_RSET

0.1

µF

0.1

µF0.1µF

AD9549

Figure 13: Phase Detector Pin Connections

DIGITAL LOOP FILTER COEFFICIENTS

In order to provide the desired flexibility, the loop filter has

been designed with three programmable coefficients (α, β and

γ). The coefficients along with P (where P=2Pio) completely

defines the response of the filter, which is given by:

(

)

(

)

(

)

(

)

(

−

LoopFilter

To evaluate the response in terms of absolute frequency

substitute:

ω 2

Where P is the divide ratio of the "P"-divider, fS is the DAC

sample rate, and f is the frequency at which the function is to be

evaluated.

AD9549 bảng dữ liệu(PDF) 28 Page - Analog Devices

AD9549 bảng dữ liệu(HTML) 28 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

bảng dữ liệu tải về

Link URL