AD9549 datasheet(40/78 Pages) AD

40 / 78 page

AD9549

Preliminary Technical Data

Rev. PrA | Page 40 of 78

images of the base band signal that theoretically extend to

infinity. Notice that the odd images (shown in Figure 25 below)

are mirror images of the base band signal. Furthermore, the

entire DAC output spectrum is affected by a sin(x)/x response,

which is caused by the "sample and hold" nature of the DAC

output signal.

Magnitude

(dB)

S/2

-100

-20

-40

-60

-80

sin(x)/x

envelope

Image 0Image 1Image 2

Image 3Image 4

primary

signal

base band

spurs

filter

response

Figure 25: DAC Spectrum vs. Reconstruction Filter Response

The response of the reconstruction filter should preserve the

base band signal (image 0), while completely rejecting all other

images. However, a practical filter implementation will

typically exhibit a relatively flat pass band that covers the

desired output frequency plus 20%, roll off as steeply as

possible, and then maintain significant (though not complete)

rejection of the remaining images.

Plot 13: DAC Output without Reconstruction Filter.

fOUT=155.52 MHz. Sysclk=25 MHz.

Sysclk PLL = x40. Spur reduction disabled.

DPLL Loop Closed. Freq Span for Plot: 500 MHz.

Plot 14: Filtered DAC Output Using 7th order elliptical with Fc=186

MHz. Same Conditions as previous plot.

Since the DAC output signal serves as the feedback signal for

the digital PLL, the design of the reconstruction filter can have a

significant impact on the overall jitter performance. Hence,

good filter design and implementation techniques are

important for obtaining the best possible jitter results.

Use of Narrowband Filter for High Performance

A distinct advantage of the AD9549 architecture is its ability to

constrain the frequency output range of the DDS. This allows

the user to employ a narrow band reconstruction filter instead

of the low pass response shown above resulting in less jitter on

the output. For example, suppose that the nominal output

frequency of the DDS is 150MHz. One might then choose a

5MHz narrow band filter centered at 150MHz. By using the

AD9549's DDS frequency limiting feature, the user could

constrain the output frequency to 150MHz ± 4.9MHz (which

allows for a 100kHz margin at the pass band edges). This will

ensure that a feedback signal is always present for the digital

PLL. Such a design would be extremely difficult to implement

with conventional PLL architectures.

AD9549 bảng dữ liệu(PDF) 40 Page - Analog Devices

AD9549 bảng dữ liệu(HTML) 40 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

bảng dữ liệu tải về

Link URL