ADFS7124-4BBCPZ datasheet(92/93 Pages) AD

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Data Sheet

ADFS7124-4

ON-CHIP REGISTERS

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Rev. 0 | 92 of 93

OFFSET REGISTERS

RS[5:0] = 1, 0, 1, 0, 0, 1 to 1, 1, 0, 0, 0, 0

Power-On/Reset = 0x800000

The ADFS7124-4 has eight offset registers, OFFSET_0 to OFFSET_7. Each offset register is associated with a setup; OFFSET_x is associated

with Setup x. The offset registers are 24-bit registers and hold the offset calibration coefficient for the ADC and its power-on reset value is

0x800000. Each of these registers is a read/write register. These registers are used in conjunction with the associated gain register to form a

register pair. The power-on reset value is automatically overwritten if an internal or system zero-scale calibration is initiated. The ADC must be

placed in the standby mode or idle mode when writing to the offset registers.

GAIN REGISTERS

RS[5:0] = 1, 1, 0, 0, 0, 1 to 1, 1, 1, 0, 0, 0

Power-On/Reset = 0x5XXXXX

The ADFS7124-4 has eight gain registers, GAIN_0 to GAIN_7. Each gain register is associated with a setup; GAIN_x is associated with Setup

x. The gain registers are 24-bit registers and hold the full-scale calibration coefficient for the ADC. The ADFS7124-4 is factory calibrated

to a gain of 1. The gain register contains this factory generated value on power-on and after a reset. The gain registers are read/write

registers. However, when writing to the registers, the ADC must be placed in the standby mode or idle mode. The default value is automatically

overwritten if an internal or system full-scale calibration is initiated or the full-scale registers are written to.

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