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ADFS7124-4BBCPZ bảng dữ liệu(PDF) 85 Page - Analog Devices

tên linh kiện ADFS7124-4BBCPZ
Giải thích chi tiết về linh kiện  4-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference
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ADFS7124-4BBCPZ bảng dữ liệu(HTML) 85 Page - Analog Devices

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Data Sheet
ADFS7124-4
ON-CHIP REGISTERS
analog.com
Rev. 0 | 85 of 93
Table 68. IO_CONTROL_1 Register Bit Descriptions (Continued)
Bits
Bit Name
Description
1101 = reserved
1110 = IOUT0 is available on the AIN6 pin.
1111 = IOUT0 is available on the AIN7 pin.
IO_CONTROL_2 REGISTER
RS[5:0] = 0, 0, 0, 1, 0, 0 Power-On/Reset = 0x0000
Table 69 outlines the bit designations for the register. Bit 15 is the first bit of the data stream. The number in parentheses indicates the
power-on/reset default status of that bit. The internal bias voltage can be enabled on multiple channels.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VBIAS7 (0)
VBIAS6 (0)
0 (0)
0 (0)
VBIAS5 (0)
VBIAS4 (0)
0 (0)
0 (0)
0 (0)
0 (0)
VBIAS3 (0)
VBIAS2 (0)
0 (0)
0 (0)
VBIAS1 (0)
VBIAS0 (0)
Table 69. IO_CONTROL_2 Register Bit Descriptions
Bits
Bit Name
Description
15
VBIAS7
Enable the bias voltage on the AIN7 channel. When set, the internal bias voltage is available on AIN7.
14
VBIAS6
Enable the bias voltage on the AIN6 channel. When set, the internal bias voltage is available on AIN6.
13, 12
0
This bit must be programmed with a Logic 0 for correct operation.
11
VBIAS5
Enable the bias voltage on the AIN5 channel. When set, the internal bias voltage is available on AIN5.
10
VBIAS4
Enable the bias voltage on the AIN4 channel. When set, the internal bias voltage is available on AIN4.
9, 8, 7, 6
0
This bit must be programmed with a Logic 0 for correct operation.
5
VBIAS3
Enable the bias voltage on the AIN3 channel. When set, the internal bias voltage is available on AIN3.
4
VBIAS2
Enable the bias voltage on the AIN2 channel. When set, the internal bias voltage is available on AIN2.
3, 2
0
This bit must be programmed with a Logic 0 for correct operation.
1
VBIAS1
Enable the bias voltage on the AIN1 channel. When set, the internal bias voltage is available on AIN1.
0
VBIAS0
Enable the bias voltage on the AIN0 channel. When set, the internal bias voltage is available on AIN0.
ID REGISTER
RS[5:0] = 0, 0, 0, 1, 0, 1 Power-On/Reset = 0x07
The identification number for the ADFS7124-4 is stored in the ID register. This is a read only register.
ERROR REGISTER
RS[5:0] = 0, 0, 0, 1, 1, 0
Power-On/Reset = 0x000000
Diagnostics, such as checking overvoltages and checking the SPI, are included on the ADFS7124-4. The error register contains the flags for
the different diagnostic functions. The functions are enabled and disabled using the ERROR_EN register.
Table 70 outlines the bit designations for the register. Bit 23 is the first bit of the data stream. The number in parentheses indicates the
power-on/reset default status of that bit.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0 (0)
LDO_CAP_ERR
(0)
ADC_CAL_ERR
(0)
ADC_CONV_ERR
(0)
ADC_SAT_ERR (0)
AINP_OV_ERR (0)
AINP_UV_ERR (0)
AINM_OV_ERR (0)
AINM_UV_ERR
(0)
REF_DET_ERR
(0)
0 (0)
DLDO_PSM_ERR
(0)
0 (0)
ALDO_PSM_ERR
(0)
SPI_IGNORE_ERR
(0)
SPI_SCLK_CNT_ERR
(0)
SPI_READ_ERR
(0)
SPI_WRITE_ERR
(0)
SPI_CRC_ERR
(0)
MM_CRC_ERR (0) ROM_CRC_ERR
(0)



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