ADFS7124-4BBCPZ datasheet(39/93 Pages) AD

39 / 93 page

Data Sheet

ADFS7124-4

GETTING STARTED

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Rev. 0 | 39 of 93

CONFIGURATION OVERVIEW

After power-on or reset, the ADFS7124-4 default configuration is as

follows:

►

Channel: Channel 0 is enabled, AIN0 is selected as the positive

input, and AIN1 is selected as the negative input. Setup 0 is

selected.

►

Setup: The input and reference buffers are disabled, the gain is

set to 1, and the external reference is selected.

►

ADC control: The ADFS7124-4 is in the low power mode, contin-

uous conversion mode, and the internal oscillator is enabled and

selected as the controller clock source.

►

Diagnostics: The only diagnostic enabled is the SPI_IG-

NORE_ERR function.

Note that only a few of the register setting options are shown; this

list is just an example. For full register information, see the On-Chip

Registers section.

Figure 68 shows an overview of the suggested flow for changing

the ADC configuration, divided into the following blocks:

►

Channel configuration (see Box A in Figure 68)

►

Setup (see Box B in Figure 68)

►

Diagnostics (see Box C in Figure 68)

►

ADC control (see Box D in Figure 68)

Channel Configuration

The ADFS7124-4 has 16 independent analog input channels and

eight independent setups. Select any of the analog input pairs on

any channel, as well as any of the eight setups for any channel,

giving full flexibility in the channel configuration. This also allows

per channel configuration when using all differential inputs because

each channel can have its own dedicated setup.

Along with the analog inputs, signals such as the power supply

or reference can also be used as inputs; they are routed to the

multiplexer internally when selected. The ADFS7124-4 allows the

user to define 16 configurations, or channels, to the ADC. This

allows diagnostics to be interleaved with conversions.

Channel Registers

Use the channel registers to select which input pins are either the

positive analog input or the negative analog input for that channel.

This register also contains a channel enable/disable bit and the

setup selection bits, which are used to select the eight available

setups to use for this channel.

When the ADFS7124-4 is operating with more than one channel

enabled, the channel sequencer cycles through the enabled chan-

nels in sequential order, from Channel 0 to Channel 15. If a channel

is disabled, it is skipped by the sequencer. Details of the channel

Figure 68. Suggested ADC Configuration Flow

Table 39. Channel 0 Register

Reg. Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

0x09

CHANNEL_0

[15:8] Enable

Setup

AINP[4:3]

0x8001

[7:0]

AINP[2:0]

AINM[4:0]

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