ES9033 datasheet(81/103 Pages) ESS

tên linh kiện	ES9033

Giải thích chi tiết về linh kiện	32-bit High-Performance 2-Channel DAC with Line Drivers

PDF	103 Pages

Scroll/Zoom	100%

nhà sản xuất	ESS [ESS Technology,Inc]

Trang chủ	http://www.esstech.com

Logo

81 / 103 page

0.3.1

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800

ES9033 Datasheet Information

PLL Registers

Note: some registers have an implied value that is recommended for normal and optimized operation.

Bits

[7]

[6]

[5:3]

[2]

[1]

[0]

Default

1’b0

3’d0

1’b0

1’b1

Bits

Mnemonic

Description

[7]

AO_SOFT_RESET

Performs soft reset to Slave Registers.

•

1’b0: Disabled (default)

•

1’b1: Enabled

[6]

PLL_SOFT_RESET

Performs soft reset to Synchronous Slave Registers.

•

1’b0: Disabled (default)

•

1’b1: Enabled

[5:3]

PLL_VCO_I

Set Current in PLL VCO

•

Must set to 3’b110, for normal operation

[2]

RESERVED

[1]

GPIO1_SDB_SYNC

Configures GPIO1 SDB (Shutdown_b). When SYS_CLK is

provided through GPIO1, set this bit to ‘1’ to allow SYS_CLK

input.

•

1’b0: Disabled (default)

•

1’b1: Enabled

[0]

PLL_CLKHV_PHASE

Digital/analog DAC clock phase control.

•

1’b0: Digital/analog DAC clocks have inverted phase

•

1’b1: Digital/analog DAC clocks have the same phase

(default)

ES9033 bảng dữ liệu(PDF) 81 Page - ESS Technology,Inc

ES9033 bảng dữ liệu(HTML) 81 Page - ESS Technology,Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL