DSP56004ROM datasheet(15/82 Pages) FREESCALE

15 / 82 page

Signal/Connection Descriptions

Interrupt and Mode Control

MOTOROLA

DSP56004/D, Rev. 3

1-9

MODC

NMI

Input,

edge-

triggered

Input (MODC) Mode Select C—This input signal has two functions:

•

to work with the MODA and MODB signals to select

the DSP’s initial operating mode, and

•

to allow an external device to request a DSP

interrupt after internal synchronization.

MODC is read and internally latched in the DSP when the

processor exits the Reset state. The logic state present on the

MODA, MODB, and MODC pins selects the initial DSP

operating mode. Several clock cycles after leaving the Reset

state, the MODC signal changes to the Non-Maskable

Interrupt request, NMI. The DSP operating mode can be

changed by software after reset.

Non-Maskable Interrupt Request

—The NMI input is a

negative-edge-triggered external interrupt request. This is a

level 3 interrupt that can not be masked out. Triggering

occurs at a voltage level and is not directly related to the fall

time of the interrupt signal. However, as the fall time of the

interrupt signal increases, the probability that noise on NMI

will generate multiple interrupts also increases. Hardware

reset causes this input to function as MODC.

RESET

input

active

RESET

—This input causes a direct hardware reset of the

processor. When RESET is asserted, the DSP is initialized and

placed in the Reset state. A Schmitt-trigger input is used for

noise immunity. When the reset signal is deasserted, the initial

DSP operating mode is latched from the MODA, MODB, and

MODC signals. The DSP also samples the PINIT signal and

writes its status into the PEN bit of the PLL Control Register.

When the DSP comes out of the Reset state, deassertion

occurs at a voltage level and is not directly related to the rise

time of the RESET signal. However, the probability that

noise on RESET will generate multiple resets increases with

increasing rise time of the RESET signal.

For proper hardware reset to occur, the clock must be active,

since a number of clock ticks are required for proper

propagation of the hardware Reset state.

Table 1-7

Interrupt and Mode Control Signals (Continued)

Signal Name

Signal

Type

State during

Reset

Signal Description

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

DSP56004ROM bảng dữ liệu(PDF) 15 Page - Freescale Semiconductor, Inc

DSP56004ROM bảng dữ liệu(HTML) 15 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

bảng dữ liệu tải về

Link URL