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UPD17062 bảng dữ liệu(PDF) 170 Page - Renesas Technology Corp |
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UPD17062 bảng dữ liệu(HTML) 170 Page - Renesas Technology Corp |
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170 / 298 page ![]() 168 µPD17062 Stops at the address of the HALT instruction. Holds the previous state. Holds the previous state. Holds the previous state. Operates normally. Operates normally. Operates normally. Stops operating. Operates normally. Operates normally. Operates normally. Holds the same state as when the HALT instruction is executed. If the STOP instruction at ( is executed in place of the HALT instruction at &, all flags in the control register set up at #, $, and % are initialized, and therefore, the serial communication is suspended and all pins of port 0A are specified as general-purpose input/output ports. Table 13-1 Behavior of the Device at the Halt and Clock Stop States Peripheral hardware State CE pin = low level Halt Clock stop Clock stop Halt CE pin = high level Program counter System register Peripheral hardware register Control register Timer A/D converter D/A converter Serial interface General-purpose input/output port General-purpose input port General-purpose output port IDC Initialized to 0000H and stops. InitializedNote. Holds the previous state. InitializedNote. Stops operating. Stops operating. Stops operating. Stops operating. Works as input port. Works as input port. Holds the previous state. Stops operating. Note See Chapters 8 and 9 for the initial values. The STOP instruction is invalid (NOP). Stops at the address of the HALT instruction. Holds the previous state. Holds the previous state. Holds the previous state. Operates normally. Operates normally. Operates normally. Stops operating. Operates normally. Operates normally. Operates normally. Stops operating. |
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