NAND02G-B2C datasheet(38/62 Pages) STMICROELECTRONICS

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Software algorithms

NAND01G-B2B, NAND02G-B2C

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8.3

Garbage Collection

When a data page needs to be modified, it is faster to write to the first available page, and

the previous page is marked as invalid. After several updates it is necessary to remove

invalid pages to free some memory space.

To free this memory space and allow further program operations it is recommended to

implement a Garbage Collection algorithm. In a Garbage Collection software the valid

pages are copied into a free area and the block containing the invalid pages is erased (see

Figure 16).

8.4

Wear-leveling algorithm

For write-intensive applications, it is recommended to implement a Wear-leveling Algorithm

to monitor and spread the number of write cycles per block.

In memories that do not use a Wear-Leveling Algorithm not all blocks get used at the same

rate. Blocks with long-lived data do not endure as many write cycles as the blocks with

frequently-changed data.

The Wear-leveling Algorithm ensures that equal use is made of all the available write cycles

for each block. There are two wear-leveling levels:

●

First Level Wear-leveling, new data is programmed to the free blocks that have had the

fewest write cycles

●

Second Level Wear-leveling, long-lived data is copied to another block so that the

original block can be used for more frequently-changed data.

The Second Level Wear-leveling is triggered when the difference between the maximum

and the minimum number of write cycles per block reaches a specific threshold.

8.5

Error Correction Code

An Error Correction Code (ECC) can be implemented in the NAND Flash memories to

identify and correct errors in the data.

For every 2048 bits in the device it is recommended to implement 22 bits of ECC (16 bits for

line parity plus 6 bits for column parity).

An ECC model is available in VHDL or Verilog. Contact the nearest ST Microelectronics

sales office for more details.

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