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UPD9993 bảng dữ liệu(PDF) 80 Page - Renesas Technology Corp

tên linh kiện UPD9993
Giải thích chi tiết về linh kiện  MOS INTEGRATED CIRCUIT
PDF  102 Pages
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nhà sản xuất  RENESAS [Renesas Technology Corp]
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UPD9993 bảng dữ liệu(HTML) 80 Page - Renesas Technology Corp

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µ PD9993
Data Sheet S17306EJ2V0DS
78
10.4 Relationship between Setting Modes and Internal Operations (Relationship with Synchronization Clock)
Table 10-1. Relationship between Setting Modes and Internal Operations (Relationship with Synchronization Clock)
Register
Pin (Signal) Status
Function
MS
SLSOR
CE[1:0]
STASI STASO LRCLK,
BCLK
Sync.
Frame
Clock
ASI
ASO
LINE_
OUT
Actual Use
Remark
Both ASI and
ASO standby
0
slave
00
synth
0
off
0
off
Input
Internal
Invalid
Hi-Z
OUT
Sound
generator-
DAC
Even though slave mode has
been set, the internal clock
operates.
ASI standby,
ASO output
0
slave
00
synth
0
off
1
on
Input
External
Invalid
OUT
OUT
Sound
generator-
DAC, ASO
Have to input an external
LRCLK. If the external LRCLK
signal has not yet been input,
output is stopped.
Both ASI and
ASO standby
0
slave
10
DSP
0
off
0
off
Input
Internal
Invalid
Hi-Z
OUT
DSP-DAC
Even though slave mode has
been set, the internal clock
operates.
ASI standby,
ASO output
0
slave
10
DSP
0
off
1
on
Input
External
Invalid
OUT
OUT
DSP-DAC,
ASO
Have to input an external
LRCLK. If the external LRCLK
signal has not yet been input,
output is stopped.
ASI input,
ASO standby
0
slave
01
ASI
1
on
0
off
Input
External
IN
Hi-Z
OUT
ASI-DAC
Have to input an external
LRCLK. If the external LRCLK
signal has not yet been input,
output is stopped.
ASI input,
ASO output
0
slave
01
ASI
1
on
1
on
Input
External
IN
OUT
OUT
ASI-DAC,
ASO
Have to input an external
LRCLK. If the external LRCLK
signal has not yet been input,
output is stopped.
Both ASI and
ASO standby
1
master
00
synth
0
off
0
off
Low
output
Internal
Invalid
Hi-Z
OUT
Sound
generator-
DAC
The internal clock operates.
ASI standby,
ASO output
1
master
00
synth
0
off
1
on
Signal
output
Internal
Invalid
OUT
OUT
Sound
generator-
DAC, ASO
The internal clock operates.
Both ASI and
ASO standby
1
master
10
DSP
0
off
0
off
Low
output
Internal
Invalid
Hi-Z
OUT
DSP-DAC
The internal clock operates.
ASI standby,
ASO output
1
master
10
DSP
0
off
1
on
Signal
output
Internal
Invalid
OUT
OUT
DSP-DAC,
ASO
The internal clock operates.
ASI input,
ASO standby
1
master
01
ASI
1
on
0
off
Signal
output
Internal
IN
Hi-Z
OUT
ASI-DAC
The internal clock operates.
ASI input,
ASO output
1
master
01
ASI
1
on
1
on
Signal
output
Internal
IN
OUT
OUT
ASI-DAC,
ASO
The internal clock operates.
Remark
The operations in Table 10-1 apply to the operations in mixing mode (address 05H, MIX = 1). Therefore,
when setting mixing (MIX = 1) while the ASIO is in slave mode (address 08H, MS = 0), be sure to set STASI
= 1 and input BCLK and LRCLK.
When stopping the ASI input and using the sound generator only, retain the settings of MS = 1, MIX = 1,
and STASI = 1 or set MIX = 0 and SLSORCE[1:0] = 00.



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