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UPD9993 bảng dữ liệu(PDF) 49 Page - Renesas Technology Corp |
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UPD9993 bảng dữ liệu(HTML) 49 Page - Renesas Technology Corp |
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49 / 102 page ![]() µ PD9993 Data Sheet S17306EJ2V0DS 47 7.3.12 INT_DSP_B enable (IDSPEN) This register enables the INT_DSP_B pin. Address: 70H, register name: IDSPEN, block: DSP, access: R/W, initial value: 00H D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 IDSPEN (1) IDSPEN Data Mode Initial Value Description 0 Disable High-level output. Interrupts of DSP are output from INT_SG_B pin. 1 Enable 0 Enables the output of interrupt signal from DSP. 7.3.13 Bank register (BANK) This register is used to switch the sound generator register bank, chip control register bank, and DSP register bank in serial I/F mode. This register is available in serial I/F mode only (it is only valid when PS = 1). Address: 4FH, register name: BANK, CPU interface, access: R/W, initial value: 01H D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 BANK (1) BANK Data Mode Initial Value Description BANK 01H Bank register for switching among sound generator register bank, DSP register bank, and chip control register bank. When BANK = 00B, the sound generator register bank is selected. When BANK = 01B, the chip control register bank is selected. When BANK = 10B, the DSP register bank is selected. Bank register can be accessed from all register banks. |
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