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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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UPD9993 bảng dữ liệu(PDF) 39 Page - Renesas Technology Corp |
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UPD9993 bảng dữ liệu(HTML) 39 Page - Renesas Technology Corp |
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39 / 102 page  µ PD9993 Data Sheet S17306EJ2V0DS 37 7. REGISTERS The µPD9993 has three register areas as follows. • Registers for PCM sound generator • Registers for chip control • Registers for DSP (MP3/AAC decoder) The registers for chip control and the DSP are described below. Caution Information on sound generator (SG) registers will be disclosed only to parties that have signed an NDA (non disclosure agreement). 7.1 Parallel I/F Mode In parallel I/F mode, the register area is switched by the combination of the A1 and A2 pins. • A1 = 0 and A2 = 0 : Chip control register • A1 = 0 and A2 = 1 : DSP for MP3/AAC decoder • A1 = 1 and A2 = 0 : PCM sound generator Remark A1 = 1 and A2 = 1 : Prohibited The register map when the PS pin is low level is as follows. 7.1.1 Register map for chip control Table 7-1. List of Control Registers (1/2) Address W/R D7 D6 D5 D4 D3 D2 D1 D0 Initial Value Control Description Register Name 00H W/R STDIG STPLL2 STPLL1 STASI STASO STSYNTH STDAC STDSP 00H LSI standby setting STNBY 01H W/R MCLK1A[7:0] 40H Master clock setting 1 MCLK1A 02H W/R MCLK1B[7:0] 79H Master clock setting 1 MCLK1B 03H W/R 0 0 0 MCLK2A[4:0] 05H Master clock setting 2 MCLK2A 04H W/R MCLK2B[7:0] 3FH Master clock setting 2 MCLK2B 05H W/R 0 0 0 MIX 0 0 SLSORCE[1:0] 00H Source selection and mixing settings SLSORCE 06H W/R 0 0 0 DVXSL 0 0 ENSRD[1:0] 00H Surround control ENSRD 07H W/R BFS[4:0] FS[2:0] 00H Sampling frequency setting and ASIO BCLK setting SLFS 08H W/R 0 0 0 0 SLR MS ASIM LRCLK 00H ASI format setting SLASI 09H W/R 0 0 0 DAULGA[4:0] 02H Digital volume (L) DAULGA 0AH W/R 0 0 0 DAURGA[4:0] 02H Digital volume (R) DAURGA 0BH W/R 0 0 0 AAULGA[4:0] 1FH Analog volume (L) AAULGA 0CH W/R 0 0 0 AAURGA[4:0] 1FH Analog volume (R) AAURGA 0DH W/R 0 0 0 0 0 0 VIB LED 00H LED, VIB port output setting VIB 0EH W/R 0 0 0 0 POUT3 POUT2 POUT1 POUT0 00H General-purpose port output setting POUT 0FH W/R 0 0 0 0 0 0 SVOL[1:0] 00H Digital Soft Volume setting SVOL Remark Don't access an unspecified address (address area is from 00H to 7FH). |
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